example_designs: add core example

example_designs/make.py

@@ -68,6 +68,10 @@ if __name__ == "__main__":
     else:
         top_class = target_module.default_subtarget
 
+    if hasattr(top_class, "platform"):
+        platform = top_class.platform
+        platform_name = top_class.platform.name
+    else:
         if args.platform is None:
             if hasattr(top_class, "default_platform"):
                 platform_name = top_class.default_platform
@@ -83,11 +87,14 @@ if __name__ == "__main__":
     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
     soc = top_class(platform, **top_kwargs)
     soc.finalize()
+    try:
         memory_regions = soc.get_memory_regions()
         csr_regions = soc.get_csr_regions()
+    except:
+        pass
 
     # decode actions
-    action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
+    action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
     actions = {k: False for k in action_list}
     for action in args.action:
         if action in actions:
@@ -108,11 +115,17 @@ if __name__ == "__main__":
    A small footprint and configurable embedded FPGA
        logic analyzer core powered by Migen
 
-====== Building parameters: ======
+====== Building parameters: ======""")
+if hasattr(soc, "io"):
+    print("""
 LiscopeIO
 ---------
 Width: {}
+""".format(soc.io.dw)
+)
 
+if hasattr(soc, "la"):
+    print("""
 LiscopeLA
 ---------
 Width: {}
@@ -120,7 +133,6 @@ Depth: {}
 Subsampler: {}
 RLE: {}
 ===============================""".format(
-    soc.io.dw,
     soc.la.dw,
     soc.la.depth,
     str(soc.la.with_subsampler),
@@ -144,6 +156,19 @@ RLE: {}
         csr_csv = cpuif.get_csr_csv(csr_regions)
         write_to_file(args.csr_csv, csr_csv)
 
+    if actions["build-core"]:
+        ios = soc.get_ios()
+        if not isinstance(soc, _Fragment):
+            soc = soc.get_fragment()
+        platform.finalize(soc)
+        so = {
+            NoRetiming:             XilinxNoRetiming,
+            MultiReg:               XilinxMultiReg,
+            AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
+        }
+        v_output = verilog.convert(soc, ios, special_overrides=so)
+        v_output.write("build/litescope.v")
+
     if actions["build-bitstream"]:
         build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
         vns = platform.build(soc, build_name=build_name, **build_kwargs)

example_designs/targets/core.py

@@ -0,0 +1,71 @@
+from migen.genlib.io import CRG
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from mibuild.generic_platform import *
+from mibuild.xilinx.platform import XilinxPlatform
+
+from targets import *
+
+from misoclib.soc import SoC
+from litescope.common import *
+from litescope.core.port import LiteScopeTerm
+from litescope.frontend.io import LiteScopeIO
+from litescope.frontend.la import LiteScopeLA
+
+
+_io = [
+    ("sys_clk", 0, Pins("X")),
+    ("sys_rst", 1, Pins("X")),
+    ("serial", 0,
+        Subsignal("tx", Pins("X")),
+        Subsignal("rx", Pins("X")),
+    ),
+    ("bus", 0, Pins(" ".join(["X" for i in range(128)])))
+]
+
+from misoclib.com.uart.bridge import UARTWishboneBridge
+
+class CorePlatform(XilinxPlatform):
+    name = "core"
+    default_clk_name = "sys_clk"
+    def __init__(self):
+        XilinxPlatform.__init__(self, "", _io)
+
+    def do_finalize(self, *args, **kwargs):
+        pass
+
+
+class Core(SoC):
+    platform = CorePlatform()
+    csr_map = {
+        "la":    16
+    }
+    csr_map.update(SoC.csr_map)
+
+    def __init__(self, platform, clk_freq=100*1000000):
+        self.clk_freq = clk_freq
+        self.clock_domains.cd_sys = ClockDomain("sys")
+        SoC.__init__(self, platform, clk_freq,
+            cpu_type="none",
+            with_csr=True, csr_data_width=32,
+            with_uart=False,
+            with_identifier=True,
+            with_timer=False
+        )
+        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_wb_master(self.cpu_or_bridge.wishbone)
+
+        self.bus = platform.request("bus")
+        self.submodules.la = LiteScopeLA((self.bus), 512, with_rle=True, with_subsampler=True)
+        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
+
+    def get_ios(self):
+        ios = set()
+        ios = ios.union({self.cd_sys.clk,
+                         self.cd_sys.rst})
+        ios = ios.union({self.platform.lookup_request("serial").rx,
+                         self.platform.lookup_request("serial").tx})
+        ios = ios.union({self.bus})
+        return ios
+
+default_subtarget = Core

test/Makefile

@@ -4,3 +4,4 @@ PYTHON = python3
 example_designs:
 	cd ../example_designs && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream
 	cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
+	cd ../example_designs && $(PYTHON) make.py -t core build-core