example_designs: keep up to date with litex

2017-09-25 12:54:25 +02:00 · 2017-09-25 12:54:25 +02:00 · d5887a3eb0
parent d4d63d7474
commit d5887a3eb0
1 changed files with 2 additions and 6 deletions
--- a/example_designs/make.py
+++ b/example_designs/make.py
@ -160,12 +160,8 @@ Depth: {}
    if actions["build-core"]:
        soc_fragment = soc.get_fragment()
        platform.finalize(soc_fragment)
-        so = {
-            NoRetiming:             XilinxNoRetimingVivado,
-            MultiReg:               XilinxMultiRegVivado,
-            AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
-        }
-        v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
+        v_output = platform.get_verilog(soc_fragment, name="litescope",
+            special_overrides=xilinx_special_overrides)
        v_output.write("build/litescope.v")

    if actions["build-bitstream"]: