Florent Kermarrec
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3efaefaae2
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example_designs: typo
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2018-06-04 08:04:10 +02:00 |
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Florent Kermarrec
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6289e81b81
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example_designs: demonstrate new features
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2018-05-28 23:43:44 +02:00 |
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Florent Kermarrec
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26a8b8989b
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example_designs: update
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2018-05-28 18:05:31 +02:00 |
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Florent Kermarrec
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9d5e605df3
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replace litex.gen imports with migen imports
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2018-02-23 13:43:47 +01:00 |
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Florent Kermarrec
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b57a5f9369
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example_design: demonstrate how to use groups, create separate capture for vcd (bus support) and sigrok (no bus support)
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2017-06-22 19:12:33 +02:00 |
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Florent Kermarrec
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01eabb2d0d
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example_design: update with litex and fix
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2017-06-22 17:58:19 +02:00 |
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Florent Kermarrec
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2f625c58b2
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update litex uart
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2017-04-19 10:46:17 +02:00 |
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Florent Kermarrec
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b1b9e61ecf
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gateware: complete refactoring (only keep essential features, now less than 200 LOCs :)
use new LiteX features and only keep one trigger, subsampler, cdc, converter and storage modules.
software still needs to be cleaned up.
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2016-03-31 21:41:51 +02:00 |
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Florent Kermarrec
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83e06cad80
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example_designs: change the way we build cores (ensure consistent IO naming)
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2015-12-27 15:42:37 +01:00 |
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Florent Kermarrec
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d0b4688184
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remove Counter module
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2015-11-24 21:50:01 +01:00 |
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Florent Kermarrec
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92c7af04db
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example_designs/targets/core: use new Pins from LiteX (allow int parameters)
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2015-11-19 15:00:18 +01:00 |
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Florent Kermarrec
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24ef9d7ebe
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for now use our fork of migen
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2015-11-13 15:46:08 +01:00 |
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Florent Kermarrec
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947d974d0a
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start adapting to new migen/litex
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2015-11-12 01:04:28 +01:00 |
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Florent Kermarrec
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7623739f5a
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change names of frontend modules: io --> inout, la--> logic_analyzer
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2015-09-27 18:47:30 +02:00 |
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Florent Kermarrec
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d4c4bb2c01
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example_designs: add core example
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2015-09-12 18:37:37 +02:00 |
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Florent Kermarrec
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9393fee9f3
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init repo
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2015-09-09 08:24:08 +02:00 |