Florent Kermarrec
|
3efaefaae2
|
example_designs: typo
|
2018-06-04 08:04:10 +02:00 |
|
Florent Kermarrec
|
6289e81b81
|
example_designs: demonstrate new features
|
2018-05-28 23:43:44 +02:00 |
|
Florent Kermarrec
|
26a8b8989b
|
example_designs: update
|
2018-05-28 18:05:31 +02:00 |
|
Florent Kermarrec
|
9d5e605df3
|
replace litex.gen imports with migen imports
|
2018-02-23 13:43:47 +01:00 |
|
Florent Kermarrec
|
b57a5f9369
|
example_design: demonstrate how to use groups, create separate capture for vcd (bus support) and sigrok (no bus support)
|
2017-06-22 19:12:33 +02:00 |
|
Florent Kermarrec
|
01eabb2d0d
|
example_design: update with litex and fix
|
2017-06-22 17:58:19 +02:00 |
|
Florent Kermarrec
|
2f625c58b2
|
update litex uart
|
2017-04-19 10:46:17 +02:00 |
|
Florent Kermarrec
|
b1b9e61ecf
|
gateware: complete refactoring (only keep essential features, now less than 200 LOCs :)
use new LiteX features and only keep one trigger, subsampler, cdc, converter and storage modules.
software still needs to be cleaned up.
|
2016-03-31 21:41:51 +02:00 |
|
Florent Kermarrec
|
d0b4688184
|
remove Counter module
|
2015-11-24 21:50:01 +01:00 |
|
Florent Kermarrec
|
24ef9d7ebe
|
for now use our fork of migen
|
2015-11-13 15:46:08 +01:00 |
|
Florent Kermarrec
|
947d974d0a
|
start adapting to new migen/litex
|
2015-11-12 01:04:28 +01:00 |
|
Florent Kermarrec
|
7623739f5a
|
change names of frontend modules: io --> inout, la--> logic_analyzer
|
2015-09-27 18:47:30 +02:00 |
|
Florent Kermarrec
|
9393fee9f3
|
init repo
|
2015-09-09 08:24:08 +02:00 |