69 lines
1.9 KiB
Python
69 lines
1.9 KiB
Python
from migen import *
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from migen.genlib.io import CRG
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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class LiteScopeSoC(SoCCore):
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csr_map = {
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"io": 16,
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"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
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sys_clk_freq = int((1e9/platform.default_clk_period))
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SoCCore.__init__(self, platform, sys_clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Litescope example design", ident_version=True,
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with_timer=False
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)
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# crg
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# bridge
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"),
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sys_clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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# Litescope IO
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self.submodules.io = LiteScopeIO(8)
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for i in range(8):
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try:
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self.comb += platform.request("user_led", i).eq(self.io.output[i])
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except:
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pass
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# Litescope Analyzer
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analyzer_groups = {}
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# counter group
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counter = Signal(16, name_override="counter")
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zero = Signal(name_override="zero")
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self.sync += counter.eq(counter + 1)
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self.comb += zero.eq(counter == 0)
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analyzer_groups[0] = [
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zero,
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counter
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]
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# communication group
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analyzer_groups[1] = [
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platform.lookup_request("serial").tx,
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platform.lookup_request("serial").rx,
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self.cpu_or_bridge.wishbone
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]
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# analyzer
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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default_subtarget = LiteScopeSoC
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