litex-boards/litex_boards/targets/acorn_cle_215.py

196 lines
7.7 KiB
Python
Raw Normal View History

2020-05-06 01:49:21 -04:00
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
2020-05-06 01:49:21 -04:00
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./acorn_cle_215.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
#
#.Build the kernel and load it:
# cd build/<platform>/driver/kernel
# make
# sudo ./init.sh
#
# Test userspace utilities:
# cd build/<platform>/driver/user
# make
# ./litepcie_util info
# ./litepcie_util scratch_test
# ./litepcie_util dma_test
# ./litepcie_util uart_test
2020-05-06 01:49:21 -04:00
import os
import argparse
import sys
from migen import *
from litex_boards.platforms import acorn_cle_215
from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.clock import *
from litex.soc.cores.led import LedChaser
2020-05-06 01:49:21 -04:00
from litedram.modules import MT41K512M16
2020-05-06 01:49:21 -04:00
from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.software import generate_litepcie_software
2020-05-06 01:49:21 -04:00
# CRG ----------------------------------------------------------------------------------------------
2020-06-30 11:28:13 -04:00
class CRG(Module):
2020-05-06 01:49:21 -04:00
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
2020-05-06 01:49:21 -04:00
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
2020-05-06 01:49:21 -04:00
# Clk/Rst
clk200 = platform.request("clk200")
# PLL
self.submodules.pll = pll = S7PLL()
self.comb += pll.reset.eq(self.rst)
2020-05-06 01:49:21 -04:00
pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
2020-05-06 01:49:21 -04:00
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
2020-05-06 01:49:21 -04:00
2020-06-30 11:41:57 -04:00
# BaseSoC -----------------------------------------------------------------------------------------
2020-05-06 01:49:21 -04:00
2020-06-30 11:41:57 -04:00
class BaseSoC(SoCCore):
2020-11-18 13:14:18 -05:00
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, **kwargs):
platform = acorn_cle_215.Platform()
2020-05-06 01:49:21 -04:00
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Acorn CLE 215+",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"),
2020-05-06 01:49:21 -04:00
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
2020-05-06 01:49:21 -04:00
2020-11-18 13:14:18 -05:00
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
("pcie2sata", 0,
Subsignal("tx_p", Pins("B6")),
Subsignal("tx_n", Pins("A6")),
Subsignal("rx_p", Pins("B10")),
Subsignal("rx_n", Pins("A10")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = sata_refclk,
pads = platform.request("pcie2sata"),
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
2020-05-06 01:49:21 -04:00
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)")
2020-11-18 13:14:18 -05:00
parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA)")
2020-05-06 01:49:21 -04:00
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
2020-11-18 13:14:18 -05:00
assert not (args.with_pcie and args.with_sata)
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
2020-11-18 13:14:18 -05:00
with_sata = args.with_sata,
**soc_sdram_argdict(args)
)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
2020-05-06 01:49:21 -04:00
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
2020-05-06 01:49:21 -04:00
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
2020-05-06 01:49:21 -04:00
if args.flash:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
2020-05-06 01:49:21 -04:00
if __name__ == "__main__":
main()