243 lines
8.6 KiB
Python
243 lines
8.6 KiB
Python
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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
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("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
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("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")),
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("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")),
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("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")),
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("user_sw", 3, Pins("G22"), IOStandard("LVCMOS25")),
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("user_sw", 4, Pins("H17"), IOStandard("LVCMOS25")),
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("user_sw", 5, Pins("J16"), IOStandard("LVCMOS25")),
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("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")),
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("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")),
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("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")),
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("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")),
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("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")),
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("user_btn", 3, Pins("D14"), IOStandard("LVCMOS25")),
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("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")),
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("user_btn", 5, Pins("G4"), IOStandard("LVCMOS25")),
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("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
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("oled", 0,
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Subsignal("dc", Pins("W22")),
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Subsignal("res", Pins("U21")),
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Subsignal("sclk", Pins("W21")),
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Subsignal("sdin", Pins("Y22")),
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Subsignal("vbat", Pins("P20")),
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Subsignal("vdd", Pins("V22")),
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IOStandard("LVCMOS33")
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),
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("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
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("serial", 0,
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Subsignal("tx", Pins("AA19")),
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Subsignal("rx", Pins("V18")),
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IOStandard("LVCMOS33"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M2 M5 M3 M1 L6 P1 N3 N2",
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"M6 R1 L5 N5 N4 P2 P6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G2 H4 H5 J1 K1 H3 H2 J5",
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"E3 B2 F3 D2 C2 A1 E2 B1"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("AA14")),
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Subsignal("rx", Pins("V13")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("Y14")),
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Subsignal("mdio", Pins("Y16")),
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Subsignal("mdc", Pins("AA16")),
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Subsignal("rx_ctl", Pins("W10")),
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Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
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Subsignal("tx_ctl", Pins("V10")),
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Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
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IOStandard("LVCMOS25")
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),
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("Y3"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("AA3"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("W2"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("Y2"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("U2"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("V2"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("AB12"), IOStandard("LVCMOS25")),
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Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")), # FIXME
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Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME
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),
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("W1"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("AA1"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("AB1"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("AB3"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("AB2"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME
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Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("LPC", {
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"DP0_C2M_P": "D7",
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"DP0_C2M_N": "C7",
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"DP0_M2C_P": "D9",
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"DP0_M2C_N": "C9",
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"GBTCLK0_M2C_P": "F10",
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"GBTCLK0_M2C_N": "E10",
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"LA01_CC_P": "J20",
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"LA01_CC_N": "J21",
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"LA05_P": "M21",
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"LA05_N": "L21",
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"LA09_P": "H20",
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"LA09_N": "G20",
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"LA13_P": "K17",
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"LA13_N": "J17",
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"LA17_CC_P": "B17",
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"LA17_CC_N": "B18",
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"LA23_P": "B21",
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"LA23_N": "A21",
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"LA26_P": "F18",
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"LA26_N": "E18",
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"CLK0_M2C_P": "J19",
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"CLK0_M2C_N": "A19",
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"LA02_P": "M18",
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"LA02_N": "L18",
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"LA04_P": "N20",
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"LA04_N": "M20",
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"LA07_P": "M13",
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"LA07_N": "L13",
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"LA11_P": "L14",
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"LA11_N": "L15",
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"LA15_P": "L16",
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"LA15_N": "K16",
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"LA19_P": "A18",
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"LA19_N": "A19",
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"LA21_P": "E19",
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"LA21_N": "D19",
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"LA24_P": "B15",
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"LA24_N": "B16",
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"LA28_P": "C13",
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"LA28_N": "B13",
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"LA30_P": "A13",
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"LA30_N": "A14",
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"LA32_P": "A15",
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"LA32_N": "A16",
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"LA06_P": "N22",
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"LA06_N": "M22",
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"LA10_P": "K21",
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"LA10_N": "K22",
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"LA14_P": "J22",
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"LA14_N": "H22",
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"LA18_CC_P": "D17",
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"LA18_CC_N": "C17",
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"LA27_P": "B20",
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"LA27_N": "A20",
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"CLK1_M2C_P": "C18",
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"CLK1_M2C_N": "C19",
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"LA00_CC_P": "K18",
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"LA00_CC_N": "K19",
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"LA03_P": "N18",
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"LA03_N": "N19",
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"LA08_P": "M15",
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"LA08_N": "M16",
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"LA12_P": "L19",
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"LA12_N": "L20",
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"LA16_P": "G17",
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"LA16_N": "G18",
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"LA20_P": "F19",
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"LA20_N": "F20",
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"LA22_P": "E21",
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"LA22_N": "D21",
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"LA25_P": "F16",
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"LA25_N": "E17",
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"LA29_P": "C14",
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"LA29_N": "C15",
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"LA31_P": "E13",
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"LA31_N": "E14",
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"LA33_P": "F13",
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"LA33_N": "F14",
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}
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
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except ConstraintError:
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pass
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