252 lines
8.5 KiB
Python
252 lines
8.5 KiB
Python
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# This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("P3"), IOStandard("LVDS")),
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("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
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("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
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("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
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("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
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("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
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("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
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("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
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("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
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("serial", 0,
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Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"P2 C4 E5 F5 B3 F4 B5 E4",
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"C5 E3 D5 B4 C3"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"L5 F1 K4 G1 L4 H1 G2 J3",
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"D1 C1 E2 C2 F3 A2 E1 B1"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST"),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("P19")),
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Subsignal("rx", Pins("L20")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("U17")),
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Subsignal("mdio", Pins("U18")),
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Subsignal("mdc", Pins("T18")),
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Subsignal("rx_ctl", Pins("U19")),
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Subsignal("rx_data", Pins("T20 U20 T19 R18")),
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Subsignal("tx_ctl", Pins("R20")),
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Subsignal("tx_data", Pins("N19 N20 P18 P20")),
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IOStandard("LVCMOS25")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("C20")),
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Subsignal("rx", Pins("J19")),
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IOStandard("LVCMOS25")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("F20")),
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Subsignal("mdio", Pins("H20")),
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Subsignal("mdc", Pins("G19")),
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Subsignal("rx_ctl", Pins("F19")),
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Subsignal("rx_data", Pins("G18 G16 H18 H17")),
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Subsignal("tx_ctl", Pins("E19")),
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Subsignal("tx_data", Pins("J17 J16 D19 D20")),
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IOStandard("LVCMOS25")
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),
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("ext_clk", 0,
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Subsignal("p", Pins("A4")),
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Subsignal("n", Pins("A5")),
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IOStandard("LVDS")
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),
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("pcie_x1", 0,
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Subsignal("clk_p", Pins("Y11")),
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Subsignal("clk_n", Pins("Y12")),
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Subsignal("rx_p", Pins("Y5")),
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Subsignal("rx_n", Pins("Y6")),
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Subsignal("tx_p", Pins("W4")),
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Subsignal("tx_n", Pins("W5")),
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Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
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),
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]
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_ecp5_soc_hat_io = [
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("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"C6 E15 A16 B16 D15 C15 B15 E12",
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"D12 B10 C7 A9 C10")),
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Subsignal("dq", Pins(
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"B19 B12 B9 E6 D6 E7 D7 B11",
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"C14 A14 E13 D13 C13 B13 A13 A12")),
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Subsignal("we_n", Pins("E9")),
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Subsignal("ras_n", Pins("B8")),
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Subsignal("cas_n", Pins("D9")),
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Subsignal("cs_n", Pins("C8")),
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Subsignal("cke", Pins("D11")),
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Subsignal("ba", Pins("D8 E8")),
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Subsignal("dm", Pins("B6 D14")),
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IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("X3",
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"None", # (no pin 0)
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"None", # 1 GND
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"None", # 2 N/C
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"None", # 3 +2V5
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"B19", # 4 EXPCON_IO29
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"B12", # 5 EXPCON_IO30
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"B9", # 6 EXPCON_IO31
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"E6", # 7 EXPCON_IO32
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"D6", # 8 EXPCON_IO33
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"E7", # 9 EXPCON_IO34
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"D7", # 10 EXPCON_IO35
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"B11", # 11 EXPCON_IO36
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"B6", # 12 EXPCON_IO37
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"E9", # 13 EXPCON_IO38
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"D9", # 14 EXPCON_IO39
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"B8", # 15 EXPCON_IO40
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"C8", # 16 EXPCON_IO41
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"D8", # 17 EXPCON_IO42
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"E8", # 18 EXPCON_IO43
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"C7", # 19 EXPCON_IO44
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"C6", # 20 EXPCON_IO45
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"None", # 21 +5V
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"None", # 22 GND
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"None", # 23 +2V5
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"None", # 24 GND
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"None", # 25 +3V3
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"None", # 26 GND
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"None", # 27 +3V3
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"None", # 28 GND
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"None", # 29 EXPCON_OSC
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"None", # 30 GND
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"None", # 31 EXPCON_CLKIN
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"None", # 32 GND
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"None", # 33 EXPCON_CLKOUT
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"None", # 34 GND
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"None", # 35 +3V3
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"None", # 36 GND
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"None", # 37 +3V3
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"None", # 38 GND
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"None", # 39 +3V3
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"None", # 40 GND
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
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except ConstraintError:
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pass
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def create_programmer(self, with_ispclock=True):
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_xcf_ispclock = """
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<Device>
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<SelectedProg value="FALSE"/>
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<Pos>2</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ispCLOCK</Family>
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<Name>ispPAC-CLK5406D</Name>
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<IDCode>0x00191043</IDCode>
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<Operation>Erase,Program,Verify</Operation>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Device>
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"""
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.4.1">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ECP5UM5G</Family>
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<Name>LFE5UM5G-45F</Name>
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<IDCode>0x81112043</IDCode>
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<File>{{bitstream_file}}</File>
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<Operation>Fast Program</Operation>
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</Device>{ispclock}
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
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</CableOptions>
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</ispXCF>
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""".format(ispclock=_xcf_ispclock if with_ispclock else "")
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return LatticeProgrammer(_xcf_template)
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