litex-boards/litex_boards/prog/openocd_limesdr_mini_v2.cfg

interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none

adapter_khz 25000

set _CHIPNAME ecp5
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043
Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)). python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg litex_term crossover __ _ __ _ __ / / (_) /____ \| \|/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/\|_\| Build your hardware, easily! (c) Copyright 2012-2022 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on May 3 2022 18:59:46 BIOS CRC passed (5f29afcc) LiteX git sha1: a4cc859d --=============== SoC ==================-- CPU: VexRiscv @ 80MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> ident Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29 2022-05-03 13:03:55 -04:00			`interface ftdi`
			`ftdi_vid_pid 0x0403 0x6010`
			`ftdi_channel 0`
			`ftdi_layout_init 0xfff8 0xfffb`
			`reset_config none`

			`adapter_khz 25000`

			`set _CHIPNAME ecp5`
			`jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043`