Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
This commit is contained in:
Florent Kermarrec
parent
c93b4dc4dc
commit
0ce7f8354c
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@ -152,6 +152,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── lattice_machxo3
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├── lattice_versa_ecp5
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├── linsn_rv901t
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├── limesdr_mini_v2
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├── litex_acorn_baseboard
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├── logicbone
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├── marblemini
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@ -0,0 +1,124 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk40", 0, Pins("A9"), IOStandard("LVCMOS33")),
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# Leds.
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("led_g_n", 0, Pins("R16"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
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("led_g_n", 1, Pins("M18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO4.
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("led_g_n", 2, Pins("T17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO6.
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("led_r_n", 0, Pins("V17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
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("led_r_n", 1, Pins("R18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO5.
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("led_r_n", 2, Pins("R17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO7.
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# Revision.
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("revision", 0,
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Subsignal("hardware", Pins("D4 M2 N4 J3")),
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Subsignal("bom", Pins("N1 M1 N2")),
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IOStandard("LVCMOS25")
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),
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# GPIO.
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("gpio", 0, Pins("N15 N18 N16 N17 M18 R18 T17 R17"), IOStandard("LVCMOS33")),
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("egpio", 0, Pins("A10 A8"), IOStandard("LVCMOS33")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("U17")),
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Subsignal("clk", Pins("U16")),
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Subsignal("miso", Pins("U18")),
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Subsignal("mosi", Pins("T18")),
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IOStandard("LVCMOS33"),
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),
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# I2C.
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("i2c", 0,
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Subsignal("scl", Pins("C10"), Misc("OPENDRAIN=ON")),
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Subsignal("sda", Pins("B9"), Misc("OPENDRAIN=ON")),
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IOStandard("LVCMOS33"),
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),
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# SPI.
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("spi", 0,
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# SPI.
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Subsignal("clk", Pins("M3")),
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Subsignal("lms_cs_n", Pins("N3")),
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Subsignal("dac_cs_n", Pins("L4")),
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Subsignal("mosi", Pins("L3")),
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Subsignal("miso", Pins("K3")),
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IOStandard("LVCMOS25"),
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),
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# Temperature Sensor.
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("lms75_os", 0, Pins("K2"), IOStandard("LVCMOS25")),
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# USB-FIFO.
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("usb_fifo_clk", 0, Pins("D17"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst_n", Pins("M17")),
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Subsignal("data", Pins(
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"A13 B12 B15 C12 A16 A12 D18 B17",
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"F15 D16 D15 C13 H18 B13 J18 A15",
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"B18 C18 A17 K18 C15 L18 F18 C16",
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"G16 D13 G18 F16 C17 F17 K15 K17")),
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Subsignal("be", Pins("L15 J17 K16 H17")),
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Subsignal("rxf_n", Pins("H16")),
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Subsignal("txe_n", Pins("M16")),
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Subsignal("rd_n", Pins("H15")),
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Subsignal("wr_n", Pins("J16")),
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Subsignal("oe_n", Pins("L16")),
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IOStandard("LVCMOS33"),
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),
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# RF-IC / LMS7002M.
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("lms7002m", 0,
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# Control.
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Subsignal("pwrdwn_n", Pins("C8")),
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Subsignal("rxen", Pins("D6")),
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Subsignal("txen", Pins("B7")),
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# RX-Interface (LMS -> FPGA).
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Subsignal("diq1", Pins("J2 L1 K1 K4 G3 F4 J1 H1 G4 F2 G1 H2")),
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Subsignal("txnrx1", Pins("F1")),
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Subsignal("iqsel1", Pins("F3")),
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Subsignal("mclk1", Pins("H4")),
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Subsignal("fclk1", Pins("H3")),
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# RX-Interface (FPGA -> LMS).
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Subsignal("diq2", Pins("A3 C2 A2 B4 C3 B2 D3 B1 A4 C1 C7 A6")),
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Subsignal("txnrx2", Pins("B6")),
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Subsignal("iqsel2", Pins("C4")),
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Subsignal("mclk2", Pins("D2")),
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Subsignal("fclk2", Pins("D1")),
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# IOStandard/Slew Rate.
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IOStandard("LVCMOS25"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk40"
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default_clk_period = 1e9/40e6
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def __init__(self, device="LFE5U", toolchain="trellis", **kwargs):
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assert device in ["LFE5U"]
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LatticePlatform.__init__(self, device + "-45F-8MG285C", _io, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_limesdr_mini_v2.cfg")
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def do_finalize(self, fragment):
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self.add_period_constraint(self.lookup_request("clk40", loose=True), 1e9/40e6)
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@ -0,0 +1,10 @@
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 25000
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set _CHIPNAME ecp5
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043
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@ -0,0 +1,165 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./limesdr_mini_v2.py --csr-csv=csr.csv --build --load
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# litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
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# litex_term crossover
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from migen import *
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from litex_boards.platforms import limesdr_mini_v2
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import stream
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.usb_fifo import FT245PHYSynchronous
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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# # #
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# Clk.
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clk40 = platform.request("clk40")
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# PLL.
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk40, 40e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# USB.
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self.comb += self.cd_usb.clk.eq(platform.request("usb_fifo_clk"))
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# BoardInfo ----------------------------------------------------------------------------------------
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class BoardInfo(Module, AutoCSR):
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def __init__(self, revision_pads):
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self.revision = CSRStorage(fields=[
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CSRField("hardware", size=4, description="Hardware Revision."),
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CSRField("bom", size=4, description="Bill of Material Revision."),
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])
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# # #
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self.comb += self.revision.fields.hardware.eq(revision_pads.hardware)
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self.comb += self.revision.fields.bom .eq(revision_pads.bom)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis",
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with_usb_fifo = True, with_usb_fifo_loopback=False,
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with_led_chaser = True,
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**kwargs):
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platform = limesdr_mini_v2.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LimeSDR-Mini-V2", **kwargs)
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# JTAGBone ---------------------------------------------------------------------------------
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self.add_jtagbone()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Info -------------------------------------------------------------------------------------
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self.submodules.info = BoardInfo(platform.request("revision"))
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# I2C Bus ----------------------------------------------------------------------------------
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# - Temperature Sensor (LM72 @ 0x48).
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# - Eeprom (M24128 @ 0x50) / Not populated.
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self.submodules.i2c = I2CMaster(platform.request("i2c"))
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# USB-FIFO ---------------------------------------------------------------------------------
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if with_usb_fifo:
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usb_pads = platform.request("usb_fifo")
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self.submodules.usb_phy = usb_phy = FT245PHYSynchronous(
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pads = usb_pads,
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clk_freq = sys_clk_freq,
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fifo_depth = 8,
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read_time = 128,
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write_time = 128,
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)
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if with_usb_fifo_loopback:
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usb_loopback = stream.SyncFIFO([("data", 32)], 2048, buffered=True)
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self.submodules += usb_loopback
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self.comb += [
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usb_phy.source.connect(usb_loopback.sink),
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usb_loopback.source.connect(usb_phy.sink),
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]
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else:
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self.comb += usb_phy.source.ready.eq(1) # Accept incoming stream to validate Host -> FPGA.
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analyzer_probes = usb_phy.get_litescope_probes()
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_probes,
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depth = 512,
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clock_domain = "usb",
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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# Debug -------------------------------------------------------------------------------
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egpio_pads = platform.request("egpio")
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self.comb += egpio_pads[0].eq(ClockSignal("sys"))
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self.comb += egpio_pads[1].eq(ClockSignal("usb"))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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leds_g = Signal(4)
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leds_r = Signal(4)
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self.comb += platform.request_all("led_g_n").eq(~leds_g)
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self.comb += platform.request_all("led_r_n").eq(~leds_r)
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self.submodules.leds = LedChaser(Cat(leds_g, leds_r), sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on LimeSDR-Mini-V2")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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toolchain = args.toolchain,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
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if __name__ == "__main__":
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main()
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