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targets: Fix targets that not using full imports.

This commit is contained in:
Florent Kermarrec 2022-05-03 18:41:18 +02:00
parent 683226df34
commit c93b4dc4dc
2 changed files with 2 additions and 4 deletions
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2
litex_boards/targets/rcs_arctic_tern_bmc_card.py
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@ -11,8 +11,6 @@
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import versa_ecp5
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex_boards.platforms import rcs_arctic_tern_bmc_card

4
litex_boards/targets/sipeed_tang_nano_9k.py
View File

@ -8,7 +8,7 @@
from migen import *
from litex_boards.platforms import tang_nano_9k
from litex_boards.platforms import sipeed_tang_nano_9k
from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
from litex.soc.integration.soc_core import *
@ -46,7 +46,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(27e6), bios_flash_offset=0x0,
with_led_chaser=True, **kwargs):
platform = tang_nano_9k.Platform()
platform = sipeed_tang_nano_9k.Platform()
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)