78 lines
2.9 KiB
Python
78 lines
2.9 KiB
Python
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#!/usr/bin/env python3
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# License: BSD
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import argparse
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import importlib
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from migen import *
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from migen.genlib.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy import LiteEthPHY
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from liteeth.mac import LiteEthMAC
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(1e9/platform.default_clk_period)
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_main_ram_size=16*1024,
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**kwargs)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
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platform.request("eth"))
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Generic LiteX SoC")
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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parser.add_argument("platform",
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help="module name of the platform to build for")
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parser.add_argument("--gateware-toolchain", default=None,
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help="FPGA gateware toolchain used for build")
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args = parser.parse_args()
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platform_module = importlib.import_module(args.platform)
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if args.gateware_toolchain is not None:
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platform = platform_module.Platform(toolchain=args.gateware_toolchain)
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else:
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platform = platform_module.Platform()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(platform, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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