Arnaud Durand 618f41bb1e Update ecp5_evn.py ... The system clock was driven directly while it should be driven by the PLL.		2019-08-22 02:27:50 +02:00
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community	Update ecp5_evn.py	2019-08-22 02:27:50 +02:00
official	keep up to date with LiteX	2019-08-07 08:47:08 +02:00
partner	partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design)	2019-08-07 09:08:11 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00