275 lines
12 KiB
Python
275 lines
12 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board product page: https://www.alientek.com/productinfo/945752.html
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# Taobao item: https://item.taobao.com/item.htm?id=641238123452
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# The Taobao agent I used: https://www.basetao.com/?ejATJf+gGuEbpa8IBg
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alientek_davincipro
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn, GPIOTristate
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litedram.modules import IS43TR16128B
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True, with_hdmi=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_eth = ClockDomain()
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if with_hdmi:
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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if with_dram:
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk50 = platform.request("clk50")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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if with_hdmi:
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self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
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self.comb += pll2.reset.eq(rst | self.rst)
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pll2.register_clkin(clk50, 50e6)
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pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll2.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
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with_xadc = False,
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with_dna = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_phy = "rgmii",
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eth_ip = "192.168.1.50",
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remote_ip = None,
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eth_dynamic_ip = False,
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with_pcie = False,
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with_led_chaser = True,
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with_buttons = True,
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with_gpio = False,
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with_video_colorbars = False,
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with_video_framebuffer = False,
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with_video_terminal = False,
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**kwargs):
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platform = alientek_davincipro.Platform(variant=variant, toolchain=toolchain)
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with_hdmi = with_video_colorbars or with_video_framebuffer or with_video_terminal
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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self.crg = _CRG(platform, sys_clk_freq, with_dram, with_rst=True, with_hdmi=with_hdmi)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on Alientek DaVinci Pro ({variant}t)", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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if with_xadc:
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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if with_dna:
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = IS43TR16128B(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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# RGMII Ethernet PHY -------------------------------------------------------------------
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if eth_phy == "rgmii":
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# phy
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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# 1000BaseX Ethernet PHY ---------------------------------------------------------------
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if eth_phy == "1000basex":
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# phy
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
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qpll_settings = QPLLSettings(
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refclksel = 0b001,
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fbdiv = 4,
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fbdiv_45 = 5,
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refclk_div = 1)
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refclk125 = self.platform.request("gtp_refclk")
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refclk125_se = Signal()
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self.specials += \
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Instance("IBUFDS_GTE2",
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i_CEB = 0,
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i_I = refclk125.p,
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i_IB = refclk125.n,
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o_O = refclk125_se)
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qpll = QPLL(refclk125_se, qpll_settings)
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self.submodules += qpll
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self.ethphy = A7_1000BASEX(
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qpll_channel = qpll.channels[0],
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_ethmac=with_ethernet)
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elif with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, local_ip=eth_ip if not eth_dynamic_ip else None, remote_ip=remote_ip)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"),
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data_width = 64,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# HDMI Options -----------------------------------------------------------------------------
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if with_hdmi:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq,
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(
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pads = platform.request_all("user_btn"),
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with_irq = self.irq.enabled
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)
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# GPIOs ------------------------------------------------------------------------------------
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if with_gpio:
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platform.add_extension(alientek_davincipro.raw_j3())
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self.gpio = GPIOTristate(
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pads = platform.request("J3"),
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with_irq = self.irq.enabled
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=alientek_davincipro.Platform, decription="LiteX SoC on Alientek Davinci Pro.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-xadc", action="store_true", help="Enable 7-Series XADC.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--with-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_xadc = args.with_xadc,
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with_dna = args.with_dna,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_buttons = True,
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with_gpio = args.with_gpio,
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with_pcie = args.with_pcie,
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with_video_colorbars = args.with_video_colorbars,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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