Gwenhael Goavec-Merou 70fb3de96c targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU		2024-06-19 07:59:24 +02:00
..
platforms	litex_acorn_baseboard_mini: Fix and test PCIe Gen2 X1 with it.	2024-06-18 09:14:08 +02:00
prog	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
targets	targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU	2024-06-19 07:59:24 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00