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litex_acorn_baseboard_mini: Fix and test PCIe Gen2 X1 with it.

This commit is contained in:
Florent Kermarrec 2024-06-18 09:14:08 +02:00
parent 27b99d4169
commit 805a520b5a
2 changed files with 6 additions and 6 deletions
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10
litex_boards/platforms/sqrl_acorn.py
View File

@ -43,13 +43,13 @@ _io = [
# PCIe.
("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
("pcie_x1_baseboard", 0,
Subsignal("rst_n", Pins("A15"), IOStandard("LVCMOS15"), Misc("PULLUP=TRUE")),
Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8")),
Subsignal("rx_n", Pins("A8")),
Subsignal("tx_p", Pins("B4")),
Subsignal("tx_n", Pins("A4")),
Subsignal("rx_p", Pins("D9")),
Subsignal("rx_n", Pins("C9")),
Subsignal("tx_p", Pins("D7")),
Subsignal("tx_n", Pins("C7")),
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS15"), Misc("PULLUP=TRUE")),

2
litex_boards/targets/litex_acorn_baseboard_mini.py
View File

@ -142,7 +142,7 @@ class BaseSoC(SoCCore):
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]")
# Ethernet / SATA RefClk/Shared-QPLL -------------------------------------------------------