2019-06-24 06:13:30 -04:00
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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2019-06-10 11:09:51 -04:00
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# clock
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("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
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# leds
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("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
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# flash
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("flash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("vpp", Pins("P21")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33")
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),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("E14")),
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Subsignal("rx", Pins("E13")),
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IOStandard("LVCMOS33"),
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),
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# dram
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("ddram", 0,
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Subsignal("a", Pins(
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"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
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"AB2 Y3 W6 Y1 V2 AA3"
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),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"N2 M6 P1 N5 P2 N4 R1 P6 "
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"K3 M2 K4 M3 J6 L5 J4 K6 "
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),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
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Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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# ethernet
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("D17")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("F16")),
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Subsignal("rx_data", Pins("A20 B18")),
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Subsignal("crs_dv", Pins("C20")),
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Subsignal("tx_en", Pins("A19")),
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Subsignal("tx_data", Pins("C18 C19")),
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Subsignal("mdc", Pins("F14")),
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Subsignal("mdio", Pins("F13")),
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Subsignal("rx_er", Pins("B20")),
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Subsignal("int_n", Pins("D21")),
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IOStandard("LVCMOS33")
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),
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# sdcard
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("sdcard", 0,
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Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
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Subsignal("clk", Pins("K18")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 20.0
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
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