litex-boards/test/test_targets.py

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# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
# License: BSD
import subprocess
import unittest
import os
from migen import *
from litex.soc.integration.builder import *
RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
def build_test(socs):
errors = 0
for soc in socs:
os.system("rm -rf build")
builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
builder.build()
errors += not os.path.isfile("./build/gateware/top.v")
os.system("rm -rf build")
return errors
class TestTargets(unittest.TestCase):
# Build simple design for all platforms
def test_simple(self):
platforms = []
# Xilinx Spartan6
platforms.append("linsn_rv901t")
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platforms.append("minispartan6")
platforms.append("pipistrello")
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platforms.append("sp605")
# Xilinx Spartan7
platforms.append("arty_s7")
# Xilinx Artix7
platforms.append("ac701")
platforms.append("aller")
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platforms.append("arty")
platforms.append("mimas_a7")
platforms.append("netv2")
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platforms.append("nexys4ddr")
platforms.append("nexys_video")
platforms.append("tagus")
platforms.append("acorn_cle_215")
platforms.append("marblemini")
# Xilinx Kintex7
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platforms.append("genesys2")
platforms.append("kc705")
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platforms.append("kx2")
platforms.append("nereid")
# Xilinx Virtex7
platforms.append("vc707")
# Xilinx Kintex Ultrascale
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platforms.append("kcu105")
# Xilinx Zynq Ultrascale+
platforms.append("zcu104")
# Xilinx Virtex Ultrascale+
platforms.append("vcu118")
# Intel Cyclone4
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platforms.append("de0nano")
platforms.append("de2_115")
# Intel Cyclone5
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platforms.append("de1soc")
platforms.append("de10nano")
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# Intel Cyclone10
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platforms.append("c10lprefkit")
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# Intel Max10
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platforms.append("de10lite")
# Lattice iCE40
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platforms.append("fomu_evt")
platforms.append("fomu_hacker")
platforms.append("fomu_pvt")
platforms.append("tinyfpga_bx")
# Lattice MachXO2
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platforms.append("machxo3")
# Lattice ECP5
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platforms.append("ecp5_evn")
platforms.append("hadbadge")
platforms.append("orangecrab")
platforms.append("trellisboard")
platforms.append("ulx3s")
platforms.append("versa_ecp5")
platforms.append("colorlight_5a_75b")
# Microsemi PolarFire
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platforms.append("avalanche")
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for name in platforms:
with self.subTest(platform=name):
cmd = """\
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litex_boards/targets/simple.py litex_boards.platforms.{} \
--no-compile-software \
--no-compile-gateware \
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--uart-name="stub" \
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""".format(name)
subprocess.check_call(cmd, shell=True)