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Merge pull request #207 from hplp/master 

Minor fixes for AU280 [work in progress]
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enjoy-digital 2021-05-03 10:20:34 +02:00 committed by GitHub
parent 2c5bf95f70 4f45462b95
commit 026c623e17
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 11 additions and 7 deletions
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2
README.md
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@ -95,7 +95,7 @@ PCIe accelerators boards that you could use to accelerate your applications, Lit
| ForestKitten33 | Xilinx Ultrascale+ | XCVU33P | 125MHz | PCIe | 2 x 1024-bit 4GB HBM2*| Gen3 X16 | ? |
| BCU1525 | Xilinx Ultrascale+ | XCVU9P | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen3 X16 | ? |
| AlveoU250 | Xilinx Ultrascale+ | XCU250 | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen2 X16 | ? |
| AlveoU280 | Xilinx Ultrascale+ | XCU280 | 125MHz | PCIe* | 2 x 64-bit DDR4 DIMM* & HBM2* | Gen2 X16 | ? |
| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit DDR4 DIMM <BR> 2 x 1024-bit 4GB HBM2* | Gen2 X16 | ? |
\* Present on the board but not yet supported or validated with LiteX.

16
litex_boards/targets/xilinx_alveo_u280.py
View File

@ -57,12 +57,12 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led=False, **kwargs):
platform = alveo_u280.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Alveo U280",
ident = "LiteX SoC on Alveo U280 (ES1)",
ident_version = True,
**kwargs)
@ -73,8 +73,9 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel),
memtype = "DDR4",
cmd_latency = 1, # seems to work better with cmd_latency=1
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
iodelay_clk_freq = 600e6,
is_rdimm = True)
self.add_sdram("sdram",
phy = self.ddrphy,
@ -94,9 +95,10 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("gpio_led"),
sys_clk_freq = sys_clk_freq)
if with_led:
self.submodules.leds = LedChaser(
pads = platform.request_all("gpio_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
@ -108,6 +110,7 @@ def main():
parser.add_argument("--ddram-channel",default="0", help="DDRAM channel (default: 0)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--with-led", action="store_true", help="Enable LED Chaser")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
@ -116,6 +119,7 @@ def main():
sys_clk_freq = int(float(args.sys_clk_freq)),
ddram_channel = int(args.ddram_channel, 0),
with_pcie = args.with_pcie,
with_led = args.with_led,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))