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litex-boards
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Merge branch 'master' of https://github.com/litex-hub/litex-boards

This commit is contained in:
Sergiu Mosanu 2021-04-29 15:41:03 -04:00
parent 8ad91d9eb3 9686db0ed3
commit 4f45462b95
5 changed files with 45 additions and 25 deletions
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12
litex_boards/platforms/siglent_sds1104xe.py
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@ -36,12 +36,12 @@ _io = [ # Documented by https://github.com/360nosc0pe project.
# LCD
("lcd", 0,
Subsignal("clk", Pins("D20")),
Subsignal("vsync", Pins("A21")),
Subsignal("hsync", Pins("A22")),
Subsignal("r", Pins("D22 D21 C22 C20 B22 B21")),
Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")),
Subsignal("b", Pins("G22 F22 F21 F19 F18 F17")),
Subsignal("clk", Pins("D20")),
Subsignal("vsync_n", Pins("A21")),
Subsignal("hsync_n", Pins("A22")),
Subsignal("r", Pins("D22 D21 C22 C20 B22 B21")),
Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")),
Subsignal("b", Pins("G22 F22 F21 F19 F18 F17")),
IOStandard("LVCMOS33"),
),

7
litex_boards/targets/antmicro_lpddr4_test_board.py
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@ -91,9 +91,14 @@ class BaseSoC(SoCCore):
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
pads = self.platform.request("eth"),
rx_delay = 0.8e-9,
)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:

37
litex_boards/targets/siglent_sds1104xe.py
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@ -8,7 +8,7 @@
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./sds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load
# ./siglent_ds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load
#
# Test Ethernet:
# ping 192.168.1.50
@ -29,7 +29,7 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoDVIPHY
from litex.soc.cores.video import VideoVGAPHY
from litedram.modules import MT41K64M16
from litedram.phy import s7ddrphy
@ -59,7 +59,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_dvi, 40e6)
pll.create_clkout(self.cd_dvi, 33.3e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
@ -107,15 +107,14 @@ class BaseSoC(SoCCore):
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
ethphy = LiteEthPHYMII(
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.submodules += ethphy
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=ethphy, dw=8,
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
@ -131,25 +130,37 @@ class BaseSoC(SoCCore):
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = ethphy.crg.cd_eth_rx.clk
eth_tx_clk = ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/ethphy.tx_clk_freq)
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", {
"pix_clk" : 33.3e6,
"h_active" : 800,
"h_blanking" : 256,
"h_sync_offset" : 210,
"h_sync_width" : 1,
"v_active" : 480,
"v_blanking" : 45,
"v_sync_offset" : 22,
"v_sync_width" : 1,
})
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoDVIPHY(platform.request("lcd"), clock_domain="dvi")
self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvi")
self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvi")
self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/sqrl_acorn.py
View File

@ -8,7 +8,7 @@
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./acorn_cle.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
# ./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
#
#.Build the kernel and load it:
# cd build/<platform>/driver/kernel

12
litex_boards/targets/terasic_sockit.py
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@ -67,11 +67,12 @@ class W9825G6KH6(SDRModule):
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"):
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_video_terminal=False):
self.sdram_rate = sdram_rate
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
if with_video_terminal:
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
if with_sdram:
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
@ -87,7 +88,10 @@ class _CRG(Module):
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_vga, 65e6)
if with_video_terminal:
pll.create_clkout(self.cd_vga, 65e6)
if with_sdram:
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
@ -117,7 +121,7 @@ class BaseSoC(SoCCore):
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate)
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal)
# SDR SDRAM --------------------------------------------------------------------------------
if mister_sdram is not None: