targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
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@ -111,7 +111,8 @@ class BaseSoC(SoCCore):
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if with_ethernet:
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYRGMII(
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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pads = self.platform.request("eth"),
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rx_delay = 0e-9)
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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self.add_ethernet(phy=self.ethphy)
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