targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).

2020-12-29 16:00:59 +01:00 · 2020-12-29 16:00:59 +01:00 · 02a81d54e2
parent 93779ecb95
commit 02a81d54e2
1 changed files with 2 additions and 1 deletions
--- a/litex_boards/targets/ecpix5.py
+++ b/litex_boards/targets/ecpix5.py
@ -111,7 +111,8 @@ class BaseSoC(SoCCore):
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYRGMII(
                clock_pads = self.platform.request("eth_clocks"),
-                pads       = self.platform.request("eth"))
+                pads       = self.platform.request("eth"),
+                rx_delay   = 0e-9)
            self.add_csr("ethphy")
            self.add_ethernet(phy=self.ethphy)