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targets/xcu1525: use ddram_channel to select clk300.

This commit is contained in:
Florent Kermarrec 2020-10-13 11:57:00 +02:00
parent 982cfd5ad5
commit 06137452d2
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/xcu1525.py
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@ -31,7 +31,7 @@ from litepcie.software import generate_litepcie_software
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq, ddram_channel):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
@ -40,7 +40,7 @@ class _CRG(Module):
# # # # # #
self.submodules.pll = pll = USPMMCM(speedgrade=-2) self.submodules.pll = pll = USPMMCM(speedgrade=-2)
pll.register_clkin(platform.request("clk300"), 300e6) pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)