targets: rename gateware-toolchain parameter to toolchain.

litex_boards/targets/camlink_4k.py

@@ -108,7 +108,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/ecp5_evn.py

@@ -64,7 +64,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_core_args(parser)
     parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)")

litex_boards/targets/hadbadge.py

@@ -80,7 +80,7 @@ class BaseSoC(SoCCore):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)")
     builder_args(parser)
     soc_sdram_args(parser)

litex_boards/targets/orangecrab.py

@@ -129,7 +129,7 @@ class BaseSoC(SoCCore):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/simple.py

@@ -47,12 +47,12 @@ def main():
     soc_core_args(parser)
     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     parser.add_argument("platform",                             help="Module name of the platform to build for")
-    parser.add_argument("--gateware-toolchain", default=None,   help="FPGA gateware toolchain used for build")
+    parser.add_argument("--toolchain", default=None,   help="FPGA gateware toolchain used for build")
     args = parser.parse_args()
 
     platform_module = importlib.import_module(args.platform)
-    if args.gateware_toolchain is not None:
-        platform = platform_module.Platform(toolchain=args.gateware_toolchain)
+    if args.toolchain is not None:
+        platform = platform_module.Platform(toolchain=args.toolchain)
     else:
         platform = platform_module.Platform()
     soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))

litex_boards/targets/trellisboard.py

@@ -125,7 +125,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/ulx3s.py

@@ -102,7 +102,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
     parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
     parser.add_argument("--sys-clk-freq", default=50e6,          help="System clock frequency (default=50MHz)")
     parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")

litex_boards/targets/versa_ecp5.py

@@ -119,7 +119,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)