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Merge pull request #130 from antmicro/fix-zybo-clock-pin 

zybo_z7: fix clock pin constraint
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enjoy-digital 2020-12-07 17:13:40 +01:00 committed by GitHub
parent 26d3b57243 f66860c201
commit 0b8a01f929
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litex_boards/platforms/zybo_z7.py
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@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# Clk / Rst
("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),