Merge pull request #130 from antmicro/fix-zybo-clock-pin
zybo_z7: fix clock pin constraint
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0b8a01f929
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@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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_io = [
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# Clk / Rst
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("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
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("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
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