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Merge pull request #347 from hplp/master 

Alveo U280 with HBM now working for Linux
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enjoy-digital 2022-02-09 07:44:36 +01:00 committed by GitHub
parent 420b9cd68d 27a7534568
commit 0c010d3d79
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3 changed files with 10 additions and 1 deletions
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3
.gitignore vendored
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@ -97,3 +97,6 @@ ENV/
# support library for EOS-S3 (downloaded when needed)
litex_boards/targets/libeos/
# ip files used during build
litex_boards/targets/ip/

2
README.md
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@ -96,7 +96,7 @@ PCIe accelerators boards that you could use to accelerate your applications, Lit
| ForestKitten33 | Xilinx Ultrascale+ | XCVU33P | 125MHz | PCIe | 2 x 1024-bit 4GB HBM2*| Gen3 X16 | ? |
| BCU1525 | Xilinx Ultrascale+ | XCVU9P | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen3 X16 | ? |
| AlveoU250 | Xilinx Ultrascale+ | XCU250 | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen2 X16 | ? |
| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit DDR4 DIMM <BR> 2 x 1024-bit 4GB HBM2* | Gen2 X16 | ? |
| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit 16GB DDR4 DIMM* <BR> 2 x 1024-bit 4GB HBM2 | Gen2 X16 | ? |
\* Present on the board but not yet supported or validated with LiteX.

6
litex_boards/targets/xilinx_alveo_u280.py
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@ -9,6 +9,9 @@
#
# SPDX-License-Identifier: BSD-2-Clause
# To interface via the serial port use:
# lxterm /dev/ttyUSBx --speed=115200
import argparse, os
from migen import *
@ -220,6 +223,9 @@ class BaseSoC(SoCCore):
axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33)
self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB.
# Link HBM2 channel 0 as main RAM
self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB.
else:
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: