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1bitsquared_icebreaker: Add test code to use LiteSPI. 

Both XiP from SPI(1X) or QSPI(4X) are working, but resource usage is currently
too high to be able to switch to it by default. We'll first try to reduce it.

Resource usage using SPI(1X) and actual LiteX SPI Flash core:
Info: Device utilisation:
Info: 	         ICESTORM_LC:  2016/ 5280    38%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%


Resource usage using LiteSPI:
Info: Device utilisation:
Info: 	         ICESTORM_LC:  3964/ 5280    75%
Info: 	        ICESTORM_RAM:     2/   30     6%
Info: 	               SB_IO:    15/   96    15%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     0/    1     0%
Info: 	        ICESTORM_DSP:     0/    8     0%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     0/    2     0%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     0/    1     0%
Info: 	         SB_RGBA_DRV:     0/    1     0%
Info: 	      ICESTORM_SPRAM:     4/    4   100%
This commit is contained in:
Florent Kermarrec 2021-07-27 16:50:18 +02:00
parent 0ca203487b
commit 0f648ac4ef
1 changed files with 13 additions and 1 deletions
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14
litex_boards/targets/1bitsquared_icebreaker.py
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@ -95,8 +95,20 @@ class BaseSoC(SoCCore):
self.submodules.spram = Up5kSPRAM(size=128*kB) self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB)) self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
# SPI Flash -------------------------------------------------------------------------------- # SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8) use_litespi = False
if use_litespi:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
from litespi.phy.generic import LiteSPIPHY
from litespi import LiteSPI
self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), W25Q128JV(Codes.READ_1_1_4))
self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness)
spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=W25Q128JV.total_size, cached=False)
self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
else:
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region -------------------------------------------------------------------- # Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion( self.bus.add_region("rom", SoCRegion(