[init] added colorlight i5a-907 support
This commit is contained in:
Charles-Henri Mousset
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1f6e7f36a5
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Colorlight 5A-75B PCB and IOs have been documented by @miek and @smunaut:
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# https://github.com/q3k/chubby75/tree/master/5a-75b
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_v7_0 = [ # Documented by @miek
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# Clk
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# Led
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("user_led_n", 0, Pins("P11"), IOStandard("LVCMOS33")),
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# Button
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("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-)
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Subsignal("rx", Pins("M13")), # btn (J19 KEY+)
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IOStandard("LVCMOS33")
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),
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# SPIFlash (W25Q32JV)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("N8")),
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("T8")),
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Subsignal("miso", Pins("T7")),
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IOStandard("LVCMOS33"),
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),
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# SDR SDRAM (M126L6161A)
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("sdram_clock", 0, Pins("C6"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"A9 E10 B12 D13 C12 D11 D10 E9",
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"D9 B7 C8")),
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Subsignal("dq", Pins(
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"B13 C11 C10 A11 C9 E8 B6 B9",
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"A6 B5 A5 B4 B3 C3 A2 B2",
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"E2 D3 A4 E4 D4 C4 E5 D5",
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"E6 D6 D8 A8 B8 B10 B11 E11")),
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Subsignal("we_n", Pins("C7")),
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Subsignal("ras_n", Pins("D7")),
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Subsignal("cas_n", Pins("E7")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("A7")),
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# RGMII Ethernet (B50612D)
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("eth_clocks", 0,
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Subsignal("tx", Pins("M2")),
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Subsignal("rx", Pins("M1")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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#Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("N6")),
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Subsignal("rx_data", Pins("N1 M5 N5 M6")),
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Subsignal("tx_ctl", Pins("M3")),
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Subsignal("tx_data", Pins("L1 L3 P2 L4")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("M12")),
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Subsignal("rx", Pins("M16")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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#Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("L15")),
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Subsignal("rx_data", Pins("P13 N13 P14 M15")),
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Subsignal("tx_ctl", Pins("R15")),
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Subsignal("tx_data", Pins("T14 R12 R13 R14")),
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IOStandard("LVCMOS33")
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),
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# USB
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("usb", 0,
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Subsignal("d_p", Pins("M8")),
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Subsignal("d_n", Pins("R2")),
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Subsignal("pullup", Pins("P4")),
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IOStandard("LVCMOS33")
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),
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]
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# From https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.md
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_connectors_v7_0 = [
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("j1", "- "),
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("j2", "- "),
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("j3", "- "),
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("j4", "- "),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeECP5Platform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, revision="7.0", toolchain="trellis"):
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assert revision in ["6.1", "7.0", "8.0"]
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self.revision = revision
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device = {"7.0": "LFE5U-25F-6BG256C"}[revision]
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io = {"7.0": _io_v7_0 }[revision]
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connectors = {"7.0": _connectors_v7_0 }[revision]
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LatticeECP5Platform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_colorlight_5a_75b.cfg")
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def do_finalize(self, fragment):
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LatticeECP5Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
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@ -47,7 +47,7 @@ from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
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from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e, colorlight_i5a_907
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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@ -125,11 +125,13 @@ class BaseSoC(SoCCore):
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sdram_rate = "1:1",
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**kwargs):
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board = board.lower()
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assert board in ["5a-75b", "5a-75e"]
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assert board in ["5a-75b", "5a-75e", "i5a-907"]
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if board == "5a-75b":
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platform = colorlight_5a_75b.Platform(revision=revision, toolchain=toolchain)
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elif board == "5a-75e":
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platform = colorlight_5a_75e.Platform(revision=revision, toolchain=toolchain)
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elif board == "i5a-907":
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platform = colorlight_i5a_907.Platform(revision=revision, toolchain=toolchain)
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if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet):
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assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
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