target/stlv7325-v2: fix typo in eth phy delay

2023-04-28 16:56:37 -04:00 · 2023-04-28 16:56:37 -04:00 · 1f6e7f36a5
parent 1185ff51f1
commit 1f6e7f36a5
1 changed files with 2 additions and 2 deletions
--- a/litex_boards/targets/sitlinv_stlv7325_v2.py
+++ b/litex_boards/targets/sitlinv_stlv7325_v2.py
@ -112,8 +112,8 @@ class BaseSoC(SoCCore):
            self.ethphy = LiteEthPHYRGMII(
                clock_pads = self.platform.request("eth_clocks", 0),
                pads       = self.platform.request("eth", 0),
-                tx_delay = 1.48-9,
-                rx_delay = 1.48-9,
+                tx_delay = 1.48e-9,
+                rx_delay = 1.48e-9,
            )
            self.add_ethernet(phy=self.ethphy)