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platforms/alveo_u250: add clk300 clock constraints.

This commit is contained in:
Florent Kermarrec 2020-05-24 11:18:30 +02:00
parent 46f78b5002
commit 12b54a7a7f
1 changed files with 4 additions and 0 deletions
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4
litex_boards/platforms/alveo_u250.py
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@ -323,6 +323,10 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time