Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX).

This commit is contained in:
Florent Kermarrec 2022-02-14 10:45:29 +01:00
parent c0e671919d
commit 12b91eccdc
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex_boards/platforms/digilent_arty.py
View File

@ -349,8 +349,7 @@ class Platform(XilinxPlatform):
self.toolchain.additional_commands = \ self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 " ["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self): def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"