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digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX).

This commit is contained in:
Florent Kermarrec 2022-02-14 10:45:29 +01:00
parent c0e671919d
commit 12b91eccdc
1 changed files with 1 additions and 2 deletions
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litex_boards/platforms/digilent_arty.py
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@ -349,7 +349,6 @@ class Platform(XilinxPlatform):
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):