parent
610e82d774
commit
1333f89ed6
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@ -28,8 +28,6 @@ _io = [
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),
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# SDRAM
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# It may help to add a header cable to some pins to mitigate suspected electrical problems on the board
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# (especially pin 67, but adding cables to the whole addr bus seemed to be the most robust)
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("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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@ -49,7 +47,6 @@ _io = [
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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@ -20,15 +20,19 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC4M16
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from litedram.phy import GENSDRPHY
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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@ -40,15 +44,20 @@ class _CRG(Module):
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=270) # Ideally 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Ideally 90° but needs to be increased.
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, sdram_rate="1:1", **kwargs):
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platform = easyfpga.Platform()
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# Limit internal rom and sram size
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@ -62,14 +71,15 @@ class BaseSoC(SoCCore):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC4M16(sys_clk_freq, "1:1"), # Hynix HY57V641620FTP-7
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module = MT48LC4M16(sys_clk_freq, sdram_rate), # Hynix HY57V641620FTP-7
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l2_cache_size = 0
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)
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@ -85,13 +95,15 @@ def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on RZ-EasyFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sdram_rate = args.sdram_rate,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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