Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #83 from madscientist159/master 

Fix Microwatt on Versa board
This commit is contained in:
enjoy-digital 2020-06-13 11:05:24 +02:00 committed by GitHub
parent 9b45ec0f35 90092164c8
commit 1537189594
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 14 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/platforms/versa_ecp5.py
View File

@ -221,8 +221,8 @@ class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
def __init__(self, device="LFE5UM5G-45F-8BG381C", **kwargs):
LatticePlatform.__init__(self, device, _io, _connectors, **kwargs)
def create_programmer(self):
return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")

13
litex_boards/targets/versa_ecp5.py
View File

@ -73,8 +73,14 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G-45F-8BG381C", with_ethernet=False, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# Fix ROM size for Microwatt
if with_ethernet:
kwargs["integrated_rom_size"] = 0xb000
else:
kwargs["integrated_rom_size"] = 0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
@ -124,10 +130,11 @@ def main():
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
parser.add_argument("--device", default="LFE5UM5G-45F-8BG381C", help="ECP5 device (default=LFE5UM5G-45F-8BG381C)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args))
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), device=args.device, with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)