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targets: always use sys_clk_freq on SDRAM modules.

This commit is contained in:
Florent Kermarrec 2020-03-21 20:00:56 +01:00
parent 3fb3ba18e8
commit 159386e3d3
5 changed files with 5 additions and 5 deletions
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2
litex_boards/targets/c10lprefkit.py
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@ -107,7 +107,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = MT48LC16M16(self.clk_freq, "1:1"), module = MT48LC16M16(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),

2
litex_boards/targets/de0nano.py
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@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16160(self.clk_freq, "1:1"), module = IS42S16160(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),

2
litex_boards/targets/de10lite.py
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@ -95,7 +95,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16320(self.clk_freq, "1:1"), module = IS42S16320(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),

2
litex_boards/targets/de1soc.py
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@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = IS42S16320(self.clk_freq, "1:1"), module = IS42S16320(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),

2
litex_boards/targets/genesys2.py
View File

@ -59,7 +59,7 @@ class BaseSoC(SoCCore):
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J256M16(self.clk_freq, "1:4"), module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),