targets/stlv7325: Reduce sys_clk_freq to 100MHz.
See https://github.com/enjoy-digital/litedram/issues/285.
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@ -59,7 +59,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6),
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def __init__(self, sys_clk_freq=int(100e6),
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with_ethernet = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_ethernet = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_led_chaser = True,
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with_led_chaser = True,
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with_pcie = False,
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with_pcie = False,
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@ -144,7 +144,7 @@ def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325")
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parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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