targets/stlv7325: Reduce sys_clk_freq to 100MHz.

See https://github.com/enjoy-digital/litedram/issues/285.
This commit is contained in:
Florent Kermarrec 2022-02-25 09:04:07 +01:00
parent 872113e1cc
commit 1623ba5942
1 changed files with 2 additions and 2 deletions

View File

@ -59,7 +59,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), def __init__(self, sys_clk_freq=int(100e6),
with_ethernet = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_ethernet = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser = True, with_led_chaser = True,
with_pcie = False, with_pcie = False,
@ -144,7 +144,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325") parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325")
parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.") parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group() ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")