targets/sqrl_acorn/ddr3: Disable write_latency_calibration.

Introduce some memtest failures on some boards.
2022-02-23 10:38:01 +01:00 · 2022-02-23 10:38:01 +01:00 · 1717af68ac
parent 16b9e100ba
commit 1717af68ac
1 changed files with 5 additions and 4 deletions
--- a/litex_boards/targets/sqrl_acorn.py
+++ b/litex_boards/targets/sqrl_acorn.py
@ -87,10 +87,11 @@ class BaseSoC(SoCCore):
        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
-                memtype          = "DDR3",
-                nphases          = 4,
-                sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 200e6)
+                memtype                   = "DDR3",
+                nphases                   = 4,
+                sys_clk_freq              = sys_clk_freq,
+                iodelay_clk_freq          = 200e6,
+                write_latency_calibration = False)
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K512M16(sys_clk_freq, "1:4"),