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targets/sqrl_acorn/ddr3: Disable write_latency_calibration. 

Introduce some memtest failures on some boards.
This commit is contained in:
Florent Kermarrec 2022-02-23 10:38:01 +01:00
parent 16b9e100ba
commit 1717af68ac
1 changed files with 5 additions and 4 deletions
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3
litex_boards/targets/sqrl_acorn.py
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@ -90,7 +90,8 @@ class BaseSoC(SoCCore):
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6) iodelay_clk_freq = 200e6,
write_latency_calibration = False)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"), module = MT41K512M16(sys_clk_freq, "1:4"),