Initial support for STLV7325 Kintex-7 board.
This commit is contained in:
Andrew Gillham
Florent Kermarrec
parent
6661947d96
commit
174d958ca7
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Gillham <gillham@roadsign.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15"))
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),
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# TODO verify / test (in docs)
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("clk156", 0,
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Subsignal("p", Pins("D6"), IOStandard("LVDS")),
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Subsignal("n", Pins("D5"), IOStandard("LVDS")),
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),
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# TODO verify / test (in docs)
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("clk150", 0,
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Subsignal("p", Pins("F6"), IOStandard("LVDS")),
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Subsignal("n", Pins("F5"), IOStandard("LVDS")),
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),
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("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
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# active low
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("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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# active low
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("user_led_n", 0, Pins("AA2"), IOStandard("LVCMOS15")),
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("user_led_n", 1, Pins("AD5"), IOStandard("LVCMOS15")),
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("user_led_n", 2, Pins("W10"), IOStandard("LVCMOS15")),
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("user_led_n", 3, Pins("Y10"), IOStandard("LVCMOS15")),
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("user_led_n", 4, Pins("AE10"), IOStandard("LVCMOS15")),
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("user_led_n", 5, Pins("W11"), IOStandard("LVCMOS15")),
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("user_led_n", 6, Pins("V11"), IOStandard("LVCMOS15")),
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("user_led_n", 7, Pins("Y12"), IOStandard("LVCMOS15")),
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# active low
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("user_key2_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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("user_key3_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V
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# I2C
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("i2c", 0, # AT24C04
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Subsignal("scl", Pins("U19")),
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Subsignal("sda", Pins("U20")),
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IOStandard("LVCMOS25")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("M25")), # CH340_TX
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Subsignal("rx", Pins("L25")), # CH340_RX
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IOStandard("LVCMOS25")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AB7 AD11 AA8 AF10 AC7 AE11 AC8 AD8",
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"AC13 AF12 AF9 AD10 AE13 AF7 AB12"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AE8 AA7 AF13"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF8"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")), # 1R
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# Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")), # 2R
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Subsignal("dm", Pins(
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"AD16 AB16 AB19 V17 U1 AA3 AD6 AE1"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AF17 AE17 AF15 AF14 AE15 AD15 AF20 AF19",
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"AA15 AA14 AC14 AD14 AB14 AB15 AA18 AA17",
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"AC18 AD18 AC17 AB17 AA20 AA19 AD19 AC19",
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"W14 V14 V19 V18 V16 W15 W16 Y17",
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"V4 U6 U5 U2 V3 W3 U7 V6",
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"Y3 Y2 V2 V1 W1 Y1 AB2 AC2",
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"AA4 AB4 AC4 AC3 AC6 AB6 Y6 Y5",
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"AD4 AD1 AF2 AE2 AE6 AE5 AF3 AE3"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AE18 Y15 AD20 W18 W6 AB1 AA5 AF5"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19 W5 AC1 AB5 AF4"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")), # 1R
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Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")), # 1R
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# Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")), # 2R
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# Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")), # 2R
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Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")), # 1R
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# Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")), # 2R
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Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), # 1R
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# Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")), # 2R
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Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=NORMAL")
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),
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## TODO verify / test
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# # SPIFlash
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# ("spiflash", 0,
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# Subsignal("cs_n", Pins("C23")),
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# Subsignal("clk", Pins("C8")),
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# Subsignal("dq", Pins("B24 A25 B22 A22")),
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# IOStandard("LVCMOS25")
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# ),
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# Sata
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("sata", 0,
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Subsignal("rx_p", Pins("R4")),
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Subsignal("rx_n", Pins("R3")),
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Subsignal("tx_p", Pins("P2")),
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Subsignal("tx_n", Pins("P1")),
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IOStandard("LVCMOS33"),
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),
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("sata", 1,
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Subsignal("rx_p", Pins("N4")),
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Subsignal("rx_n", Pins("N3")),
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Subsignal("tx_p", Pins("M2")),
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Subsignal("tx_n", Pins("M1")),
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IOStandard("LVCMOS33"),
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("N21")),
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Subsignal("cs_n", Pins("P19")),
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Subsignal("mosi", Pins("U21"), Misc("PULLUP")),
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Subsignal("miso", Pins("N16"), Misc("PULLUP")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS25")
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),
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("sdcard", 0,
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Subsignal("clk", Pins("N21")),
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Subsignal("cmd", Pins("U21"), Misc("PULLUP True")),
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Subsignal("data", Pins("N16 U16 N22 P19"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS25")
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),
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# GMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("E12"), IOStandard("LVCMOS15")),
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Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS15")),
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Subsignal("rx", Pins("C12"), IOStandard("LVCMOS15"))
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("C9"), IOStandard("LVCMOS15")),
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Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS15")),
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Subsignal("rx", Pins("E10"), IOStandard("LVCMOS15"))
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),
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("eth", 0,
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Subsignal("rst_n", Pins("D11")),
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# Subsignal("int_n", Pins("")),
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Subsignal("mdio", Pins("K15")),
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Subsignal("mdc", Pins("M16")),
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Subsignal("rx_dv", Pins("G14")),
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Subsignal("rx_er", Pins("F14")),
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Subsignal("rx_data", Pins("H14 J14 J13 H13 B15 A15 B14 A14")),
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Subsignal("tx_en", Pins("F12")),
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Subsignal("tx_er", Pins("E13")),
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Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS15")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("J8")),
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# Subsignal("int_n", Pins("")),
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Subsignal("mdio", Pins("G9")),
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Subsignal("mdc", Pins("H8")),
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Subsignal("rx_dv", Pins("A12")),
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Subsignal("rx_er", Pins("D10")),
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Subsignal("rx_data", Pins("A13 B12 B11 A10 B10 A9 B9 A8")),
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Subsignal("tx_en", Pins("F8")),
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Subsignal("tx_er", Pins("D9")),
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Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS15")
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),
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# HDMI out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("R21"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("P21"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("N18"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("M19"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("M21"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("M22"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("K25"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("K26"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("K21"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("L23"), IOStandard("LVCMOS33")),
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Subsignal("hdp", Pins("N26"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("M26"), IOStandard("LVCMOS33")),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("H6")),
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Subsignal("clk_n", Pins("H5")),
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Subsignal("rx_p", Pins("B6")),
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Subsignal("rx_n", Pins("B5")),
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Subsignal("tx_p", Pins("A4")),
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Subsignal("tx_n", Pins("A3"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("H6")),
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Subsignal("clk_n", Pins("H5")),
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Subsignal("rx_p", Pins("B6 C4")),
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Subsignal("rx_n", Pins("B5 C3")),
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Subsignal("tx_p", Pins("A4 B2")),
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Subsignal("tx_n", Pins("A3 B1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("H6")),
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Subsignal("clk_n", Pins("H5")),
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Subsignal("rx_p", Pins("B6 C4 E4 G4")),
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Subsignal("rx_n", Pins("B5 C3 E3 G3")),
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Subsignal("tx_p", Pins("A4 B2 D2 F2")),
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Subsignal("tx_n", Pins("A3 B1 D1 F1"))
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),
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# TODO find / test
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# # SGMII Clk
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# ("sgmii_clock", 0,
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# Subsignal("p", Pins("")),
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# Subsignal("n", Pins(""))
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# ),
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# SFP
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("sfp_a", 0, # SFP A
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Subsignal("txp", Pins("H2")),
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Subsignal("txn", Pins("H1")),
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Subsignal("rxp", Pins("J4")),
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Subsignal("rxn", Pins("J3")),
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Subsignal("sda", Pins("B21")),
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Subsignal("scl", Pins("C21")),
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),
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("sfp_a_tx", 0, # SFP A
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Subsignal("p", Pins("H2")),
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Subsignal("n", Pins("H1"))
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),
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("sfp_a_rx", 0, # SFP A
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Subsignal("p", Pins("J4")),
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Subsignal("n", Pins("J3"))
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),
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("sfp_b", 0, # SFP B
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Subsignal("txp", Pins("K2")),
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Subsignal("txn", Pins("K1")),
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Subsignal("rxp", Pins("L4")),
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Subsignal("rxn", Pins("L3")),
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Subsignal("sda", Pins("D21")),
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Subsignal("scl", Pins("C22")),
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),
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("sfp_b_tx", 0, # SFP B
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Subsignal("p", Pins("K2")),
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Subsignal("n", Pins("K1"))
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),
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("sfp_b_rx", 0, # SFP B
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Subsignal("p", Pins("L4")),
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Subsignal("n", Pins("L3"))
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),
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# SI5338 (optional part per seller?)
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("si5338_i2c", 0,
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Subsignal("sck", Pins("U19"), IOStandard("LVCMOS25")),
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Subsignal("sda", Pins("U20"), IOStandard("LVCMOS25"))
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),
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("si5338_clkin", 0, # CLK2A/B
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Subsignal("p", Pins("K6"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K5"), IOStandard("LVDS_25"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# TODO; add FMC / BTB
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado")
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self.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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""")
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", 1, loose=True), 1e9/125e6)
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self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
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@ -0,0 +1,163 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Gillham <gillham@roadsign.com>
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import stlv7325
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import DDR3Module
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy import LiteEthPHY
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_led_chaser=True,
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with_pcie=False, with_sata=False, **kwargs):
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platform = stlv7325.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on STLV7325",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
|
||||
|
||||
# DDR3 SDRAM -------------------------------------------------------------------------------
|
||||
if not self.integrated_main_ram_size:
|
||||
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR3",
|
||||
nphases = 4,
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.ddrphy,
|
||||
module = MT8JTF12864(sys_clk_freq, "1:4"),
|
||||
size = 0x40000000,
|
||||
l2_cache_size = kwargs.get("l2_size", 8192)
|
||||
)
|
||||
|
||||
# Ethernet ---------------------------------------------------------------------------------
|
||||
if with_ethernet:
|
||||
self.submodules.ethphy = LiteEthPHY(
|
||||
clock_pads = self.platform.request("eth_clocks", 0),
|
||||
pads = self.platform.request("eth", 0),
|
||||
clk_freq = self.clk_freq)
|
||||
self.add_ethernet(phy=self.ethphy)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# TODO verify / test
|
||||
# SATA -------------------------------------------------------------------------------------
|
||||
if with_sata:
|
||||
from litex.build.generic_platform import Subsignal, Pins
|
||||
from litesata.phy import LiteSATAPHY
|
||||
|
||||
# RefClk, Generate 150MHz from PLL.
|
||||
self.clock_domains.cd_sata_refclk = ClockDomain()
|
||||
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
|
||||
sata_refclk = ClockSignal("sata_refclk")
|
||||
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
|
||||
|
||||
# PHY
|
||||
self.submodules.sata_phy = LiteSATAPHY(platform.device,
|
||||
refclk = sata_refclk,
|
||||
pads = platform.request("sata", 0),
|
||||
gen = "gen2",
|
||||
clk_freq = sys_clk_freq,
|
||||
data_width = 16)
|
||||
|
||||
# Core
|
||||
self.add_sata(phy=self.sata_phy, mode="read+write")
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led_n"),
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
|
||||
# I2C --------------------------------------------------------------------------------------
|
||||
self.submodules.i2c = I2CMaster(platform.request("i2c"))
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325")
|
||||
parser.add_argument("--build", action="store_true", help="Build bitstream.")
|
||||
parser.add_argument("--load", action="store_true", help="Load bitstream.")
|
||||
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
|
||||
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
|
||||
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
|
||||
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
|
||||
parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA).")
|
||||
builder_args(parser)
|
||||
soc_core_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(
|
||||
sys_clk_freq = int(float(args.sys_clk_freq)),
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_pcie = args.with_pcie,
|
||||
with_sata = args.with_sata,
|
||||
**soc_core_argdict(args)
|
||||
)
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build(run=args.build)
|
||||
|
||||
if args.driver:
|
||||
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue