mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
commit
17a0152ef9
2 changed files with 268 additions and 27 deletions
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@ -3,6 +3,7 @@
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -21,8 +22,8 @@ _io = [
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# Serial.
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("serial", 0,
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Subsignal("rx", Pins("P15")),
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Subsignal("tx", Pins("N16")),
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Subsignal("rx", Pins("N16")),
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Subsignal("tx", Pins("P15")),
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IOStandard("LVCMOS33")
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),
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@ -52,27 +53,184 @@ _io = [
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),
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("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("sdram_clock", 0, Pins("AC26"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V17 U15 V16 U16 T23 T25 R25 P25",
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"W23 V23 W21 U24 U25")),
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Subsignal("dq", Pins(
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"V22 U22 W19 V19 Y20 W20 V26 U26",
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"AB25 AB26 AA25 AA24 Y26 Y25 W26 W25")),
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Subsignal("ba", Pins("P21 Y21")),
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Subsignal("cas_n", Pins("P24")),
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Subsignal("cs_n", Pins("U14")),
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Subsignal("ras_n", Pins("P23")),
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Subsignal("we_n", Pins("R23")),
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IOStandard("LVCMOS33"),
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# DDR3 SDRAM IMD128M16R39CG8GNF-125.
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("ddram", 0,
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Subsignal("a", Pins(
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"N1 R1 R2 N2 P1 T2 N4 U1",
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"T4 T3 M1 P4 N3 U2 U5 M6"),
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IOStandard("SSTL15")
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),
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Subsignal("ba", Pins("M4 L5 K3"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("H2"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("H1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("J3"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("L4"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("F4 H9 E3 A3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G4 J6 L8 G5 K7 J5 K8 K6",
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"E6 H8 H6 G8 D6 F8 G6 F7",
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"C4 F3 B4 E5 D3 D5 A4 D4",
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"E1 A2 G2 C2 F2 E2 G1 D1"),
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IOStandard("SSTL15")),
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Subsignal("dqs_p", Pins("J4 H7 B5 C1"), IOStandard("SSTL15D")), # DRIVE=8
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Subsignal("dqs_n", Pins("H4 G7 A5 B1"), IOStandard("SSTL15D")), # DRIVE=8
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Subsignal("clk_p", Pins("M2"), IOStandard("SSTL15D")), # DRIVE=8
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Subsignal("clk_n", Pins("L2"), IOStandard("SSTL15D")), # DRIVE=8
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Subsignal("cke", Pins("L3"), IOStandard("SSTL15")), # DRIVE=4
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Subsignal("odt", Pins("J1"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N8"), IOStandard("SSTL15")),
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Misc("PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# TODO
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["J1",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND ( 1-10).
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" ---- ---- AC26 AC24 AB26 AB24 AB25 AA23 AA24 AA22",
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# GND GND ( 11-20).
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" AA25 Y23 Y25 Y22 Y26 W24 W25 V24 ---- ----",
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# ( 21-30).
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" W26 W23 V26 V23 U26 U24 U25 L24 R26 Y20",
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# ( 31-40).
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" P26 W20 P19 W19 N19 V19 M20 V22 L20 U22",
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# 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V ( 41-50).
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" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
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# 5V 5V 5V 5V 5V 5V 3V3 5V 3V3 5V ( 51-60).
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" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
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# GND GND GND ( 61-70).
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" ---- ---- R15 N16 L20 E17 ---- E18 M21 N17",
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# GND GND GND ( 71-80).
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" M22 M24 ---- M25 N23 N22 N24 N21 ---- ----",
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# ( 81-90).
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" N26 L22 M26 L23 C19 K22 D19 K23 K25 K21",
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# ( 91-100).
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" K26 J21 J25 N18 J26 M19 H26 L19 G26 K18",
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# GND GND (101-110).
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" ---- ---- M15 J24 L15 H24 K20 J23 J20 H23",
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# GND GND (111-120).
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" E26 D23 D26 D24 C26 C22 B26 C23 ---- ----",
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],
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["J2",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND VCCO VCCO VCCO VCCO GND GND ( 1-10).
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" ---- ---- ---- ---- ---- ---- ---- ---- V21 P25",
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# GND ( 11-20).
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" U21 R25 ---- T25 U20 T24 T20 T23 U19 R23",
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# GND ( 21-30).
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" T19 P24 W18 P23 V18 P21 R18 ---- T18 Y21",
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# GND ( 31-40).
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" T17 W21 U17 ---- U14 V17 V14 V16 T15 U16",
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# GND GND ( 41-50).
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" T14 U15 Y9 AB15 AB7 W9 ---- ---- R17 J15",
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# GND GND GND GND ( 51-60).
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" R16 J14 ---- ---- R11 AE16 R12 U4 ---- ----",
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# GND GND ( 61-70).
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" AD14 AA11 AC14 AB11 ---- ---- AB13 AC10 AA13 AD10",
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# GND GND GND GND ( 71-80).
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" ---- ---- AF13 Ac8 AE13 AD8 ---- ---- AF11 AE9",
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# GND GND GND GND ( 81-90).
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" AE11 AF9 ---- ---- AD12 AE7 AC12 AF7 ---- ----",
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# GND GND ( 91-100).
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" W4 AB1 V4 AC1 ---- ---- AA3 AE5 Y3 AF5",
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# GND GND GND GND (101-110).
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" ---- ---- W3 AE3 V3 AF3 ---- ---- AA2 AE2",
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# GND GND GND GND (111-120).
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" Y2 AF2 ---- ---- W1 AD1 V1 AE1 ---- ----",
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],
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["J3",
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# -------------------------------------------------------------
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"---", # 0
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# GND GND GND ( 1-10).
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" ---- ---- B25 A24 A25 A23 C24 ---- B24 H22",
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# GND GND ( 11-20).
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" E25 H21 D25 F20 G24 G19 F24 ---- ---- F19",
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# ( 21-30).
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" E22 F18 H17 M17 F23 M16 E23 J16 B22 K15",
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# GND ( 31-40).
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" A22 ---- E21 F22 D21 G22 E20 G21 D20 G20",
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# GND GND ( 41-50).
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" ---- ---- D18 H19 C18 J19 C17 F25 B17 G25",
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# GND ( 51-60).
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" E16 ---- D16 H18 G17 J18 F17 K17 L17 K16",
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# GND ( 61-70).
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" L18 F15 ---- G15 H14 G16 H15 H16 C21 L14",
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# GND GND GND ( 71-80).
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" B21 M14 B20 ---- A20 P11 ---- N12 B19 ----",
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# TCK GND TDI TDO TMS GND GND ( 81-90).
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" A19 H12 ---- H10 A17 J10 A18 H11 ---- ----",
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# GND GND ( 91-100).
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" F11 F13 E11 E13 ---- ---- D10 C12 C10 D12",
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# GND GND GND GND (101-110).
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" ---- ---- D8 C14 C8 D14 ---- ---- B9 A13",
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# GND GND GND GND (111-120).
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" A9 B13 ---- ---- B7 P11 A7 N12 ---- ----",
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],
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]
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# Dock IOs -----------------------------------------------------------------------------------------
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# Note: SOM.J1 -> dock.J6 odd/even revert
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# SOM.J2 -> dock.J7 odd/even revert
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# SOM.J3 -> dock.J8 odd/even revert
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_dock_io = [
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# HDMI In
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("J1:107")),
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Subsignal("clk_n", Pins("J1:109")),
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Subsignal("data0_p", Pins("J1:87")),
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Subsignal("data0_n", Pins("J1:85")),
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Subsignal("data1_p", Pins("J1:103")),
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Subsignal("data1_n", Pins("J1:105")),
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Subsignal("data2_p", Pins("J1:93")),
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Subsignal("data2_n", Pins("J1:95")),
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Subsignal("hdp", Pins("J1:99")),
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#Subsignal("scl", Pins("J1:89")),
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#Subsignal("sda", Pins("J1:91")),
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#Subsignal("cec", Pins("J1:97")),
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IOStandard("LVCMOS33D"),
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Misc("PULL_MODE=NONE DRIVE=8")
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("J1:14")),
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Subsignal("clk_n", Pins("J1:12")),
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Subsignal("data0_p", Pins("J1:6")),
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Subsignal("data0_n", Pins("J1:4")),
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Subsignal("data1_p", Pins("J1:18")),
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Subsignal("data1_n", Pins("J1:16")),
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Subsignal("data2_p", Pins("J1:10")),
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Subsignal("data2_n", Pins("J1:8")),
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Subsignal("hdp", Pins("J2:39")),
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#Subsignal("scl", Pins("J1:89")),
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#Subsignal("sda", Pins("J1:91")),
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#Subsignal("cec", Pins("J2:41")),
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IOStandard("LVCMOS33D"),
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Misc("PULL_MODE=NONE DRIVE=8")
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),
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("sdram_clock", 0, Pins("V23"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V19 W19 U22 V22 Y25 AA25 AA24 AB25",
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"AB26 AC26 Y20 U25 U24")),
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Subsignal("dq", Pins(
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"U16 V16 U15 V17 W21 Y21 P21 U17",
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"P25 W23 T25 R25 R23 T23 P24 P23")),
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Subsignal("ba", Pins("V26 W20")),
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Subsignal("cas_n", Pins("W26")),
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Subsignal("cs_n", Pins("U26")),
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Subsignal("ras_n", Pins("W25")),
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Subsignal("we_n", Pins("Y26")),
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IOStandard("LVCMOS33"),
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Misc("PULL_MODE=UP")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -83,6 +241,7 @@ class Platform(GowinPlatform):
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def __init__(self, dock="standard", toolchain="gowin"):
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GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B")
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self.add_extension(_dock_io)
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self.toolchain.options["use_sspi_as_gpio"] = 1
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self.toolchain.options["use_cpu_as_gpio"] = 1
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@ -5,6 +5,7 @@
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#
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# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -17,11 +18,13 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser, WS2812
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from litex.soc.cores.video import *
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from liteeth.phy.gw5rgmii import LiteEthPHYRGMII
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from litedram.modules import AS4C32M16
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from litedram.modules import AS4C32M16, MT41K64M16
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litedram.phy import GW5DDRPHY
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from litex.build.io import DDROutput
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from litex_boards.platforms import sipeed_tang_mega_138k
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@ -29,12 +32,23 @@ from litex_boards.platforms import sipeed_tang_mega_138k
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_sdram=False):
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def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_ddr3=False, with_video_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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if with_sdram:
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self.cd_sys_ps = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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if with_ddr3:
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self.cd_init = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_i = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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# Clk
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self.clk50 = platform.request("clk50")
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@ -51,15 +65,46 @@ class _CRG(LiteXModule):
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self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | self.rst | rst)
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pll.register_clkin(self.clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if with_sdram:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
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# SDRAM clock
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if with_sdram:
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sdram_clk = ClockSignal("sys_ps")
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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sdram_clk = ClockSignal("sys2x_ps")
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# DDR3 clock
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if with_ddr3:
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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self.specials += [
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Instance("DHCE",
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i_CLKIN = self.cd_sys2x_i.clk,
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i_CEN = self.stop,
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o_CLKOUT = self.cd_sys2x.clk
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),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset),
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]
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# Init clock domain
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self.comb += self.cd_init.clk.eq(self.clk50)
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self.comb += self.cd_init.rst.eq(pll.reset)
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if with_video_pll:
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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pll.create_clkout(self.cd_hdmi5x, 125e6, margin=1e-3)
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self.specials += Instance("CLKDIV",
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p_DIV_MODE = "5",
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i_HCLKIN = self.cd_hdmi5x.clk,
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i_RESETN = 1, # Disable reset signal.
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i_CALIB = 0, # No calibration.
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o_CLKOUT = self.cd_hdmi.clk
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)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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|
@ -69,7 +114,10 @@ class BaseSoC(SoCCore):
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local_ip = "192.168.1.50",
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remote_ip = "",
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eth_dynamic_ip = False,
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with_video_terminal = False,
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with_ddr3 = False,
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with_sdram = False,
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sdram_rate = "1:2",
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with_led_chaser = True,
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with_rgb_led = False,
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with_buttons = True,
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|
@ -78,11 +126,37 @@ class BaseSoC(SoCCore):
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platform = sipeed_tang_mega_138k.Platform(toolchain="gowin")
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_sdram=with_sdram)
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self.crg = _CRG(platform, sys_clk_freq,
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with_sdram = with_sdram,
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with_ddr3 = with_ddr3,
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with_video_pll = with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if with_ddr3 and not self.integrated_main_ram_size:
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self.ddrphy = GW5DDRPHY(
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pads = platform.request("ddram"),
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sys_clk_freq = sys_clk_freq
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)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K64M16(sys_clk_freq, "1:2"),
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l2_cache_size = 0#kwargs.get("l2_size", 8192)
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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hdmi_pads = platform.request("hdmi_in") # yes DVI_RX because DVI_TX seems not working
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self.comb += hdmi_pads.hdp.eq(1)
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self.videophy = VideoGowinHDMIPHY(hdmi_pads, clock_domain="hdmi")
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#self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
self.leds = LedChaser(
|
||||
|
@ -126,10 +200,14 @@ class BaseSoC(SoCCore):
|
|||
|
||||
# SDR SDRAM --------------------------------------------------------------------------------
|
||||
if with_sdram and not self.integrated_main_ram_size:
|
||||
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
|
||||
if sdram_rate == "1:2":
|
||||
sdrphy_cls = HalfRateGENSDRPHY
|
||||
else:
|
||||
sdrphy_cls = GENSDRPHY
|
||||
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.sdrphy,
|
||||
module = AS4C32M16(sys_clk_freq, "1:1"),
|
||||
module = AS4C32M16(sys_clk_freq, sdram_rate),
|
||||
l2_cache_size = kwargs.get("l2_size", 8192)
|
||||
)
|
||||
|
||||
|
@ -141,6 +219,8 @@ def main():
|
|||
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
|
||||
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
|
||||
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
|
||||
parser.add_target_argument("--with-ddr3", action="store_true", help="Enable optional DDR3 module.")
|
||||
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
|
||||
ethopts = parser.target_group.add_mutually_exclusive_group()
|
||||
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
|
||||
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
|
||||
|
@ -153,6 +233,8 @@ def main():
|
|||
|
||||
soc = BaseSoC(
|
||||
sys_clk_freq = args.sys_clk_freq,
|
||||
with_video_terminal = args.with_video_terminal,
|
||||
with_ddr3 = args.with_ddr3,
|
||||
with_sdram = args.with_sdram,
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_etherbone = args.with_etherbone,
|
||||
|
|
Loading…
Reference in a new issue