aliexpress_xc7k70t: Review/Cleanup.
- Cosmetic cleanups in platform. - Add clk50 constraint. - Remove JTAGBone specific support since now directly handled by LiteX.
This commit is contained in:
Florent Kermarrec
parent
8f43cfe18c
commit
8e3dc21ce5
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@ -97,6 +97,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── alchitry_cu
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├── alchitry_mojo
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├── aliexpress_xc7k420t
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├── aliexpress_xc7k70t
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├── alinx_ax7010
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├── alinx_axu2cga
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├── analog_pocket
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@ -42,15 +42,15 @@ _io = [
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# SDRAM
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("sdram_clock", 0, Pins("P23"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
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Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
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Subsignal("ba", Pins("K25 M24")),
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Subsignal("dm", Pins("N23 G26")),
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Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
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Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
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Subsignal("ba", Pins("K25 M24")),
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Subsignal("dm", Pins("N23 G26")),
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Subsignal("ras_n", Pins("N24")),
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Subsignal("cas_n", Pins("K26")),
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Subsignal("we_n", Pins("P26")),
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Subsignal("cs_n", Pins("N26")),
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Subsignal("cke", Pins("J25")),
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Subsignal("we_n", Pins("P26")),
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Subsignal("cs_n", Pins("N26")),
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Subsignal("cke", Pins("J25")),
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IOStandard("LVCMOS33"),
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Misc("SLEW = FAST")
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),
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@ -103,14 +103,15 @@ _io = [
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# HDMI out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("E10"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("D10"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("D9"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("D8"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("C9"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("B9"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("A9"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("A8"), IOStandard("TMDS_33")),
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Subsignal("clk_p", Pins("E10")),
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Subsignal("clk_n", Pins("D10")),
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Subsignal("data0_p", Pins("D9")),
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Subsignal("data0_n", Pins("D8")),
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Subsignal("data1_p", Pins("C9")),
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Subsignal("data1_n", Pins("B9")),
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Subsignal("data2_p", Pins("A9")),
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Subsignal("data2_n", Pins("A8")),
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IOStandard("TMDS_33"),
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),
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# PCIe
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@ -176,26 +177,26 @@ _connectors = [
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# 3.3V
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("HR_IO", {
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0 : "D19",
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1 : "D18",
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2 : "C21",
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3 : "D20",
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4 : "C22",
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5 : "D21",
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6 : "C24",
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7 : "D23",
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8 : "D24",
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9 : "A19",
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10 : "B19",
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11 : "A20",
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12 : "B20",
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13 : "B21",
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14 : "A23",
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15 : "A24",
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16 : "B25",
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17 : "B26",
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18 : "C26",
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19 : "D25",
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0 : "D19",
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1 : "D18",
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2 : "C21",
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3 : "D20",
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4 : "C22",
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5 : "D21",
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6 : "C24",
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7 : "D23",
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8 : "D24",
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9 : "A19",
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10 : "B19",
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11 : "A20",
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12 : "B20",
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13 : "B21",
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14 : "A23",
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15 : "A24",
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16 : "B25",
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17 : "B26",
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18 : "C26",
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19 : "D25",
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}),
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# 3.3V
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@ -231,7 +232,7 @@ set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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""")
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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@ -239,5 +240,6 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)
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@ -60,7 +60,6 @@ class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
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with_hdmi = False,
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with_ethernet = False,
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with_jtagbone = False,
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with_pcie = False,
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with_sdram = True,
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with_led_chaser = True,
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@ -99,10 +98,6 @@ class BaseSoC(SoCCore):
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet:
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self.ethphy = LiteEthPHYRGMII(
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@ -131,16 +126,15 @@ class BaseSoC(SoCCore):
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.")
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parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe")
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parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
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parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe")
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parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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args = parser.parse_args()
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# Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
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@ -150,7 +144,6 @@ def main():
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sdram_rate = args.sdram_rate,
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with_ethernet = args.with_ethernet,
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with_pcie = args.with_pcie,
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with_jtagbone = args.with_jtagbone,
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with_hdmi = args.with_hdmi,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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