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Merge pull request #547 from trabucayre/tangMega138k

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Tang mega138k
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enjoy-digital 2023-11-09 11:56:58 +01:00 committed by GitHub
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2 changed files with 268 additions and 27 deletions
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193
litex_boards/platforms/sipeed_tang_mega_138k.py
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@ -3,6 +3,7 @@
# #
# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me> # Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import * from migen import *
@ -21,8 +22,8 @@ _io = [
# Serial. # Serial.
("serial", 0, ("serial", 0,
Subsignal("rx", Pins("P15")), Subsignal("rx", Pins("N16")),
Subsignal("tx", Pins("N16")), Subsignal("tx", Pins("P15")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
@ -52,27 +53,184 @@ _io = [
), ),
("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")), ("ephy_clk", 0, Pins("E18"), IOStandard("LVCMOS33")),
("sdram_clock", 0, Pins("AC26"), IOStandard("LVCMOS33")), # DDR3 SDRAM IMD128M16R39CG8GNF-125.
("sdram", 0, ("ddram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(
"V17 U15 V16 U16 T23 T25 R25 P25", "N1 R1 R2 N2 P1 T2 N4 U1",
"W23 V23 W21 U24 U25")), "T4 T3 M1 P4 N3 U2 U5 M6"),
Subsignal("dq", Pins( IOStandard("SSTL15")
"V22 U22 W19 V19 Y20 W20 V26 U26", ),
"AB25 AB26 AA25 AA24 Y26 Y25 W26 W25")), Subsignal("ba", Pins("M4 L5 K3"), IOStandard("SSTL15")),
Subsignal("ba", Pins("P21 Y21")), Subsignal("ras_n", Pins("H2"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P24")), Subsignal("cas_n", Pins("H1"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("U14")), Subsignal("we_n", Pins("J3"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P23")), Subsignal("cs_n", Pins("L4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R23")), Subsignal("dm", Pins("F4 H9 E3 A3"), IOStandard("SSTL15")),
IOStandard("LVCMOS33"), Subsignal("dq", Pins(
"G4 J6 L8 G5 K7 J5 K8 K6",
"E6 H8 H6 G8 D6 F8 G6 F7",
"C4 F3 B4 E5 D3 D5 A4 D4",
"E1 A2 G2 C2 F2 E2 G1 D1"),
IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("J4 H7 B5 C1"), IOStandard("SSTL15D")), # DRIVE=8
Subsignal("dqs_n", Pins("H4 G7 A5 B1"), IOStandard("SSTL15D")), # DRIVE=8
Subsignal("clk_p", Pins("M2"), IOStandard("SSTL15D")), # DRIVE=8
Subsignal("clk_n", Pins("L2"), IOStandard("SSTL15D")), # DRIVE=8
Subsignal("cke", Pins("L3"), IOStandard("SSTL15")), # DRIVE=4
Subsignal("odt", Pins("J1"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("N8"), IOStandard("SSTL15")),
Misc("PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5"),
), ),
] ]
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
# TODO ["J1",
# -------------------------------------------------------------
"---", # 0
# GND GND ( 1-10).
" ---- ---- AC26 AC24 AB26 AB24 AB25 AA23 AA24 AA22",
# GND GND ( 11-20).
" AA25 Y23 Y25 Y22 Y26 W24 W25 V24 ---- ----",
# ( 21-30).
" W26 W23 V26 V23 U26 U24 U25 L24 R26 Y20",
# ( 31-40).
" P26 W20 P19 W19 N19 V19 M20 V22 L20 U22",
# 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V ( 41-50).
" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
# 5V 5V 5V 5V 5V 5V 3V3 5V 3V3 5V ( 51-60).
" ---- ---- ---- ---- ---- ---- ---- ---- ---- ----",
# GND GND GND ( 61-70).
" ---- ---- R15 N16 L20 E17 ---- E18 M21 N17",
# GND GND GND ( 71-80).
" M22 M24 ---- M25 N23 N22 N24 N21 ---- ----",
# ( 81-90).
" N26 L22 M26 L23 C19 K22 D19 K23 K25 K21",
# ( 91-100).
" K26 J21 J25 N18 J26 M19 H26 L19 G26 K18",
# GND GND (101-110).
" ---- ---- M15 J24 L15 H24 K20 J23 J20 H23",
# GND GND (111-120).
" E26 D23 D26 D24 C26 C22 B26 C23 ---- ----",
],
["J2",
# -------------------------------------------------------------
"---", # 0
# GND GND VCCO VCCO VCCO VCCO GND GND ( 1-10).
" ---- ---- ---- ---- ---- ---- ---- ---- V21 P25",
# GND ( 11-20).
" U21 R25 ---- T25 U20 T24 T20 T23 U19 R23",
# GND ( 21-30).
" T19 P24 W18 P23 V18 P21 R18 ---- T18 Y21",
# GND ( 31-40).
" T17 W21 U17 ---- U14 V17 V14 V16 T15 U16",
# GND GND ( 41-50).
" T14 U15 Y9 AB15 AB7 W9 ---- ---- R17 J15",
# GND GND GND GND ( 51-60).
" R16 J14 ---- ---- R11 AE16 R12 U4 ---- ----",
# GND GND ( 61-70).
" AD14 AA11 AC14 AB11 ---- ---- AB13 AC10 AA13 AD10",
# GND GND GND GND ( 71-80).
" ---- ---- AF13 Ac8 AE13 AD8 ---- ---- AF11 AE9",
# GND GND GND GND ( 81-90).
" AE11 AF9 ---- ---- AD12 AE7 AC12 AF7 ---- ----",
# GND GND ( 91-100).
" W4 AB1 V4 AC1 ---- ---- AA3 AE5 Y3 AF5",
# GND GND GND GND (101-110).
" ---- ---- W3 AE3 V3 AF3 ---- ---- AA2 AE2",
# GND GND GND GND (111-120).
" Y2 AF2 ---- ---- W1 AD1 V1 AE1 ---- ----",
],
["J3",
# -------------------------------------------------------------
"---", # 0
# GND GND GND ( 1-10).
" ---- ---- B25 A24 A25 A23 C24 ---- B24 H22",
# GND GND ( 11-20).
" E25 H21 D25 F20 G24 G19 F24 ---- ---- F19",
# ( 21-30).
" E22 F18 H17 M17 F23 M16 E23 J16 B22 K15",
# GND ( 31-40).
" A22 ---- E21 F22 D21 G22 E20 G21 D20 G20",
# GND GND ( 41-50).
" ---- ---- D18 H19 C18 J19 C17 F25 B17 G25",
# GND ( 51-60).
" E16 ---- D16 H18 G17 J18 F17 K17 L17 K16",
# GND ( 61-70).
" L18 F15 ---- G15 H14 G16 H15 H16 C21 L14",
# GND GND GND ( 71-80).
" B21 M14 B20 ---- A20 P11 ---- N12 B19 ----",
# TCK GND TDI TDO TMS GND GND ( 81-90).
" A19 H12 ---- H10 A17 J10 A18 H11 ---- ----",
# GND GND ( 91-100).
" F11 F13 E11 E13 ---- ---- D10 C12 C10 D12",
# GND GND GND GND (101-110).
" ---- ---- D8 C14 C8 D14 ---- ---- B9 A13",
# GND GND GND GND (111-120).
" A9 B13 ---- ---- B7 P11 A7 N12 ---- ----",
],
]
# Dock IOs -----------------------------------------------------------------------------------------
# Note: SOM.J1 -> dock.J6 odd/even revert
# SOM.J2 -> dock.J7 odd/even revert
# SOM.J3 -> dock.J8 odd/even revert
_dock_io = [
# HDMI In
("hdmi_in", 0,
Subsignal("clk_p", Pins("J1:107")),
Subsignal("clk_n", Pins("J1:109")),
Subsignal("data0_p", Pins("J1:87")),
Subsignal("data0_n", Pins("J1:85")),
Subsignal("data1_p", Pins("J1:103")),
Subsignal("data1_n", Pins("J1:105")),
Subsignal("data2_p", Pins("J1:93")),
Subsignal("data2_n", Pins("J1:95")),
Subsignal("hdp", Pins("J1:99")),
#Subsignal("scl", Pins("J1:89")),
#Subsignal("sda", Pins("J1:91")),
#Subsignal("cec", Pins("J1:97")),
IOStandard("LVCMOS33D"),
Misc("PULL_MODE=NONE DRIVE=8")
),
# HDMI Out
("hdmi_out", 0,
Subsignal("clk_p", Pins("J1:14")),
Subsignal("clk_n", Pins("J1:12")),
Subsignal("data0_p", Pins("J1:6")),
Subsignal("data0_n", Pins("J1:4")),
Subsignal("data1_p", Pins("J1:18")),
Subsignal("data1_n", Pins("J1:16")),
Subsignal("data2_p", Pins("J1:10")),
Subsignal("data2_n", Pins("J1:8")),
Subsignal("hdp", Pins("J2:39")),
#Subsignal("scl", Pins("J1:89")),
#Subsignal("sda", Pins("J1:91")),
#Subsignal("cec", Pins("J2:41")),
IOStandard("LVCMOS33D"),
Misc("PULL_MODE=NONE DRIVE=8")
),
("sdram_clock", 0, Pins("V23"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"V19 W19 U22 V22 Y25 AA25 AA24 AB25",
"AB26 AC26 Y20 U25 U24")),
Subsignal("dq", Pins(
"U16 V16 U15 V17 W21 Y21 P21 U17",
"P25 W23 T25 R25 R23 T23 P24 P23")),
Subsignal("ba", Pins("V26 W20")),
Subsignal("cas_n", Pins("W26")),
Subsignal("cs_n", Pins("U26")),
Subsignal("ras_n", Pins("W25")),
Subsignal("we_n", Pins("Y26")),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=UP")
),
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
@ -83,6 +241,7 @@ class Platform(GowinPlatform):
def __init__(self, dock="standard", toolchain="gowin"): def __init__(self, dock="standard", toolchain="gowin"):
GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B") GowinPlatform.__init__(self, "GW5AST-LV138FPG676AES", _io, _connectors, toolchain=toolchain, devicename="GW5AST-138B")
self.add_extension(_dock_io)
self.toolchain.options["use_sspi_as_gpio"] = 1 self.toolchain.options["use_sspi_as_gpio"] = 1
self.toolchain.options["use_cpu_as_gpio"] = 1 self.toolchain.options["use_cpu_as_gpio"] = 1

102
litex_boards/targets/sipeed_tang_mega_138k.py
View file

@ -5,6 +5,7 @@
# #
# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me> # Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import * from migen import *
@ -17,11 +18,13 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser, WS2812 from litex.soc.cores.led import LedChaser, WS2812
from litex.soc.cores.video import *
from liteeth.phy.gw5rgmii import LiteEthPHYRGMII from liteeth.phy.gw5rgmii import LiteEthPHYRGMII
from litedram.modules import AS4C32M16 from litedram.modules import AS4C32M16, MT41K64M16
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litedram.phy import GW5DDRPHY
from litex.build.io import DDROutput from litex.build.io import DDROutput
from litex_boards.platforms import sipeed_tang_mega_138k from litex_boards.platforms import sipeed_tang_mega_138k
@ -29,12 +32,23 @@ from litex_boards.platforms import sipeed_tang_mega_138k
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule): class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, with_sdram=False): def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_ddr3=False, with_video_pll=False):
self.rst = Signal() self.rst = Signal()
self.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.cd_por = ClockDomain() self.cd_por = ClockDomain()
if with_sdram: if with_sdram:
self.cd_sys_ps = ClockDomain() if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
else:
self.cd_sys_ps = ClockDomain()
if with_ddr3:
self.cd_init = ClockDomain()
self.cd_sys2x = ClockDomain()
self.cd_sys2x_i = ClockDomain()
self.stop = Signal()
self.reset = Signal()
# Clk # Clk
self.clk50 = platform.request("clk50") self.clk50 = platform.request("clk50")
@ -51,15 +65,46 @@ class _CRG(LiteXModule):
self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device) self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~por_done | self.rst | rst) self.comb += pll.reset.eq(~por_done | self.rst | rst)
pll.register_clkin(self.clk50, 50e6) pll.register_clkin(self.clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
if with_sdram:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock # SDRAM clock
if with_sdram: if with_sdram:
sdram_clk = ClockSignal("sys_ps") if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
sdram_clk = ClockSignal("sys2x_ps")
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
# DDR3 clock
if with_ddr3:
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
self.specials += [
Instance("DHCE",
i_CLKIN = self.cd_sys2x_i.clk,
i_CEN = self.stop,
o_CLKOUT = self.cd_sys2x.clk
),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset),
]
# Init clock domain
self.comb += self.cd_init.clk.eq(self.clk50)
self.comb += self.cd_init.rst.eq(pll.reset)
if with_video_pll:
self.cd_hdmi = ClockDomain()
self.cd_hdmi5x = ClockDomain()
pll.create_clkout(self.cd_hdmi5x, 125e6, margin=1e-3)
self.specials += Instance("CLKDIV",
p_DIV_MODE = "5",
i_HCLKIN = self.cd_hdmi5x.clk,
i_RESETN = 1, # Disable reset signal.
i_CALIB = 0, # No calibration.
o_CLKOUT = self.cd_hdmi.clk
)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
@ -69,7 +114,10 @@ class BaseSoC(SoCCore):
local_ip = "192.168.1.50", local_ip = "192.168.1.50",
remote_ip = "", remote_ip = "",
eth_dynamic_ip = False, eth_dynamic_ip = False,
with_video_terminal = False,
with_ddr3 = False,
with_sdram = False, with_sdram = False,
sdram_rate = "1:2",
with_led_chaser = True, with_led_chaser = True,
with_rgb_led = False, with_rgb_led = False,
with_buttons = True, with_buttons = True,
@ -78,11 +126,37 @@ class BaseSoC(SoCCore):
platform = sipeed_tang_mega_138k.Platform(toolchain="gowin") platform = sipeed_tang_mega_138k.Platform(toolchain="gowin")
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, with_sdram=with_sdram) self.crg = _CRG(platform, sys_clk_freq,
with_sdram = with_sdram,
with_ddr3 = with_ddr3,
with_video_pll = with_video_terminal)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if with_ddr3 and not self.integrated_main_ram_size:
self.ddrphy = GW5DDRPHY(
pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq
)
self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"),
l2_cache_size = 0#kwargs.get("l2_size", 8192)
)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
hdmi_pads = platform.request("hdmi_in") # yes DVI_RX because DVI_TX seems not working
self.comb += hdmi_pads.hdp.eq(1)
self.videophy = VideoGowinHDMIPHY(hdmi_pads, clock_domain="hdmi")
#self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser:
self.leds = LedChaser( self.leds = LedChaser(
@ -126,10 +200,14 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size: if with_sdram and not self.integrated_main_ram_size:
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = AS4C32M16(sys_clk_freq, "1:1"), module = AS4C32M16(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192) l2_cache_size = kwargs.get("l2_size", 8192)
) )
@ -141,6 +219,8 @@ def main():
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.") parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--with-ddr3", action="store_true", help="Enable optional DDR3 module.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
ethopts = parser.target_group.add_mutually_exclusive_group() ethopts = parser.target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
@ -153,6 +233,8 @@ def main():
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
with_video_terminal = args.with_video_terminal,
with_ddr3 = args.with_ddr3,
with_sdram = args.with_sdram, with_sdram = args.with_sdram,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,