targets/arty: sync with litex repository
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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0b8a01f929
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@ -312,12 +312,12 @@ class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="a7-35"):
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35ticsg324-1L",
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"a7-100": "xc7a100tcsg324-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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@ -331,4 +331,5 @@ class Platform(XilinxPlatform):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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from litex.build.xilinx import symbiflow
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -4,6 +4,7 @@
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -54,13 +55,13 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
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platform = arty.Platform()
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
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platform = arty.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Arty A7",
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ident_version = True,
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ident_version = ident_version,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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@ -104,13 +105,15 @@ class BaseSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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@ -118,9 +121,11 @@ def main():
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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ident_version = args.no_ident_version,
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**soc_sdram_argdict(args)
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)
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assert not (args.with_spi_sdcard and args.with_sdcard)
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@ -130,7 +135,8 @@ def main():
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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builder.build(**builder_kwargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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