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decklink_quad_hdmi_recorder: Add other DDR3 SDRAM modules building but untested.

This commit is contained in:
Florent Kermarrec 2021-06-30 11:50:42 +02:00
parent e65308ee13
commit 18b2758e4e
1 changed files with 10 additions and 4 deletions
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14
litex_boards/platforms/decklink_quad_hdmi_recorder.py
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@ -75,20 +75,26 @@ _io = [
Subsignal("cas_n", Pins("AM16"), IOStandard("SSTL15_DCI")),
Subsignal("we_n", Pins("AP15"), IOStandard("SSTL15_DCI")),
Subsignal("cs_n", Pins("AM15"), IOStandard("SSTL15_DCI")),
Subsignal("dm", Pins("AH26 AN26"),
Subsignal("dm", Pins("AH26 AN26 AJ21 AM21 AH18 AE25 AD21 AD19"),
IOStandard("SSTL15_DCI"),
Misc("DATA_RATE=DDR")),
Subsignal("dq", Pins(
"AM27 AK28 AH27 AJ28 AK26 AH28 AM26 AK27",
"AP29 AP28 AM30 AN27 AM29 AN28 AL30 AL29"),
"AP29 AP28 AM30 AN27 AM29 AN28 AL30 AL29",
"AM20 AK22 AL20 AL22 AL23 AL24 AK23 AL25",
"AP25 AM24 AN24 AM22 AN23 AN22 AP24 AP23",
"AJ16 AG17 AG15 AG19 AH16 AH19 AG14 AG16",
"AJ24 AG24 AJ23 AF23 AH22 AF24 AH23 AG25",
"AE20 AF20 AD20 AG20 AE22 AE23 AF22 AG22",
"AF18 AD15 AF17 AE17 AF14 AE18 AF15 AD16"),
IOStandard("SSTL15_DCI"),
Misc("ODT=RTT_40"),
Misc("DATA_RATE=DDR")),
Subsignal("dqs_p", Pins("AL27 AN29"),
Subsignal("dqs_p", Pins("AL27 AN29 AJ20 AP20 AJ15 AH24 AG21 AE16"),
IOStandard("DIFF_SSTL15_DCI"),
Misc("ODT=RTT_40"),
Misc("DATA_RATE=DDR")),
Subsignal("dqs_n", Pins("AL28 AP30"),
Subsignal("dqs_n", Pins("AL28 AP30 AK20 AP21 AJ14 AJ25 AH21 AE15"),
IOStandard("DIFF_SSTL15_DCI"),
Misc("ODT=RTT_40"),
Misc("DATA_RATE=DDR")),