Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/colorlight_5a_75b: update sys/sys_ps phases.

This commit is contained in:
Florent Kermarrec 2020-03-31 18:18:45 +02:00
parent 9ae8a0cc11
commit 19e5366ad1
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/targets/colorlight_5a_75b.py
View File

@ -52,8 +52,8 @@ class _CRG(Module):
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
# SDRAM clock