targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).

2025-01-03 03:43:36 -05:00 · 2021-03-29 16:03:19 +02:00 · 2021-03-29 16:03:19 +02:00 · 1ca8ef97a1
commit 1ca8ef97a1
parent ba01776432
38 changed files with 1 additions and 41 deletions
--- a/litex_boards/targets/camlink_4k.py
+++ b/litex_boards/targets/camlink_4k.py
@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K64M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@ -147,14 +147,11 @@ class BaseSoC(SoCCore):
            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
            if board == "5a-75e" and revision == "6.0":
                sdram_cls  = M12L64322A
-                sdram_size = 0x80000000
            else:
                sdram_cls  = M12L16161A
-                sdram_size = 0x40000000
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = sdram_cls(sys_clk_freq, sdram_rate),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/colorlight_i5.py
+++ b/litex_boards/targets/colorlight_i5.py
@ -134,7 +134,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = sdram_cls(sys_clk_freq, sdram_rate),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/digilent_arty.py
+++ b/litex_boards/targets/digilent_arty.py
@ -76,7 +76,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K128M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/digilent_arty_s7.py
+++ b/litex_boards/targets/digilent_arty_s7.py
@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K128M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/digilent_genesys2.py
+++ b/litex_boards/targets/digilent_genesys2.py
@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J256M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/digilent_nexys4ddr.py
+++ b/litex_boards/targets/digilent_nexys4ddr.py
@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT47H64M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/digilent_nexys_video.py
+++ b/litex_boards/targets/digilent_nexys_video.py
@ -81,7 +81,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K256M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/enclustra_mercury_kx2.py
+++ b/litex_boards/targets/enclustra_mercury_kx2.py
@ -47,7 +47,7 @@ class _CRG(Module):

 class BaseSoC(SoCCore):
    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
-        platform = kx2.Platform()
+        platform = mercury_kx2.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = H5TC4G63CFR(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/enclustra_mercury_xu5.py
+++ b/litex_boards/targets/enclustra_mercury_xu5.py
@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT40A256M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/fpc_iii.py
+++ b/litex_boards/targets/fpc_iii.py
@ -108,7 +108,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = IS43TR16256A(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )
        self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)
--- a/litex_boards/targets/gsd_orangecrab.py
+++ b/litex_boards/targets/gsd_orangecrab.py
@ -193,7 +193,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = sdram_module(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/hackaday_hadbadge.py
+++ b/litex_boards/targets/hackaday_hadbadge.py
@ -74,7 +74,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = AS4C32M8(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/kosagi_netv2.py
+++ b/litex_boards/targets/kosagi_netv2.py
@ -82,7 +82,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = K4B2G1646F(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/lambdaconcept_ecpix5.py
+++ b/litex_boards/targets/lambdaconcept_ecpix5.py
@ -100,7 +100,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K256M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/lattice_versa_ecp5.py
+++ b/litex_boards/targets/lattice_versa_ecp5.py
@ -104,7 +104,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K64M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/linsn_rv901t.py
+++ b/litex_boards/targets/linsn_rv901t.py
@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = M12L64322A(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/logicbone.py
+++ b/litex_boards/targets/logicbone.py
@ -130,7 +130,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = sdram_module(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/mist.py
+++ b/litex_boards/targets/mist.py
@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = MT48LC16M16(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/numato_aller.py
+++ b/litex_boards/targets/numato_aller.py
@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J128M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/numato_mimas_a7.py
+++ b/litex_boards/targets/numato_mimas_a7.py
@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J128M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/qmtech_ep4ce15.py
+++ b/litex_boards/targets/qmtech_ep4ce15.py
@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16160(sys_clk_freq, sdram_rate),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/qmtech_wukong.py
+++ b/litex_boards/targets/qmtech_wukong.py
@ -74,7 +74,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K128M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/saanlima_pipistrello.py
+++ b/litex_boards/targets/saanlima_pipistrello.py
@ -181,7 +181,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT46H32M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/scarabhardware_minispartan6.py
+++ b/litex_boards/targets/scarabhardware_minispartan6.py
@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy              = self.sdrphy,
                module           = AS4C16M16(sys_clk_freq, sdram_rate),
-                size             = 0x40000000,
                l2_cache_size    = kwargs.get("l2_size", 8192),
                l2_cache_reverse = False
            )
--- a/litex_boards/targets/siglent_sds1104xe.py
+++ b/litex_boards/targets/siglent_sds1104xe.py
@ -90,7 +90,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K64M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/sqrl_acorn.py
+++ b/litex_boards/targets/sqrl_acorn.py
@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K512M16(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_de0nano.py
+++ b/litex_boards/targets/terasic_de0nano.py
@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16160(sys_clk_freq, sdram_rate),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_de10lite.py
+++ b/litex_boards/targets/terasic_de10lite.py
@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16320(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_de10nano.py
+++ b/litex_boards/targets/terasic_de10nano.py
@ -83,7 +83,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = AS4C32M16(sys_clk_freq, sdram_rate),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_de1soc.py
+++ b/litex_boards/targets/terasic_de1soc.py
@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16320(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_de2_115.py
+++ b/litex_boards/targets/terasic_de2_115.py
@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16320(self.clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/terasic_sockit.py
+++ b/litex_boards/targets/terasic_sockit.py
@ -126,7 +126,6 @@ class BaseSoC(SoCCore):
        self.add_sdram("sdram",
            phy           = self.sdrphy,
            module        = sdrphy_mod(sys_clk_freq, sdram_rate),
-            size          = 0x40000000,
            l2_cache_size = kwargs.get("l2_size", 8192)
        )

--- a/litex_boards/targets/trellisboard.py
+++ b/litex_boards/targets/trellisboard.py
@ -134,7 +134,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J256M16(sys_clk_freq, "1:2"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/trenz_c10lprefkit.py
+++ b/litex_boards/targets/trenz_c10lprefkit.py
@ -81,7 +81,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = MT48LC16M16(sys_clk_freq, "1:1"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/xilinx_kc705.py
+++ b/litex_boards/targets/xilinx_kc705.py
@ -73,7 +73,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT8JTF12864(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/xilinx_vc707.py
+++ b/litex_boards/targets/xilinx_vc707.py
@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT8JTF12864(sys_clk_freq, "1:4"),
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

--- a/litex_boards/targets/ztex213.py
+++ b/litex_boards/targets/ztex213.py
@ -85,7 +85,6 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
-                size          = 0x40000000,
                l2_cache_size = kwargs.get("l2_size", 8192)
            )