targets/add_sdram: Simplify call by removing useless arguments.

- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

litex_boards/targets/camlink_4k.py

@@ -92,13 +92,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq=sys_clk_freq)
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K64M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K64M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/colorlight_5a_75x.py

@@ -152,13 +152,10 @@ class BaseSoC(SoCCore):
                 sdram_cls  = M12L16161A
                 sdram_size = 0x40000000
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = sdram_cls(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", sdram_size),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = sdram_cls(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/colorlight_i5.py

@@ -132,13 +132,10 @@ class BaseSoC(SoCCore):
             # if board == "i5" and revision == "7.0":
             sdram_cls  = M12L64322A # compat with EM638325-6H
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = sdram_cls(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = sdram_cls(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/digilent_arty.py

@@ -74,13 +74,10 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/digilent_arty_s7.py

@@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/digilent_genesys2.py

@@ -66,13 +66,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J256M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J256M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/digilent_nexys4ddr.py

@@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
                 nphases      = 2,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT47H64M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT47H64M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/digilent_nexys_video.py

@@ -79,13 +79,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K256M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K256M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/enclustra_mercury_kx2.py

@@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = H5TC4G63CFR(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = H5TC4G63CFR(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/enclustra_mercury_xu5.py

@@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT40A256M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT40A256M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/fpc_iii.py

@@ -106,13 +106,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = IS43TR16256A(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x20000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = IS43TR16256A(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
         self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)
 

litex_boards/targets/gsd_orangecrab.py

@@ -191,13 +191,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = sdram_module(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = sdram_module(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/hackaday_hadbadge.py

@@ -72,13 +72,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = AS4C32M8(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = AS4C32M8(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
 # Build --------------------------------------------------------------------------------------------

litex_boards/targets/kosagi_netv2.py

@@ -80,13 +80,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = K4B2G1646F(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = K4B2G1646F(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/lambdaconcept_ecpix5.py

@@ -98,13 +98,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K256M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K256M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -64,9 +64,9 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
     mem_map = {
-        "rom":              0x00000000,
-        "sram":             0x40000000,
-        "csr":              0xf0000000,
+        "rom"  : 0x00000000,
+        "sram" : 0x40000000,
+        "csr"  : 0xf0000000,
     }
     def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", **kwargs):
         platform = crosslink_nx_evn.Platform(toolchain=toolchain)

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -65,9 +65,9 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
     mem_map = {
-        "rom":              0x00000000,
-        "sram":             0x40000000,
-        "csr":              0xf0000000,
+        "rom":  0x00000000,
+        "sram": 0x40000000,
+        "csr":  0xf0000000,
     }
     def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs):
         platform = crosslink_nx_vip.Platform(toolchain=toolchain)

litex_boards/targets/lattice_versa_ecp5.py

@@ -102,13 +102,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K64M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K64M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/linsn_rv901t.py

@@ -66,13 +66,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = M12L64322A(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = M12L64322A(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/logicbone.py

@@ -128,13 +128,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = sdram_module(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = sdram_module(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/mist.py

@@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = MT48LC16M16(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x2000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = MT48LC16M16(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Video Terminal ---------------------------------------------------------------------------

litex_boards/targets/numato_aller.py

@@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # PCIe -------------------------------------------------------------------------------------

litex_boards/targets/numato_mimas_a7.py

@@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/numato_nereid.py

@@ -73,13 +73,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # PCIe -------------------------------------------------------------------------------------

litex_boards/targets/numato_tagus.py

@@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # PCIe -------------------------------------------------------------------------------------

litex_boards/targets/qmtech_ep4ce15.py

@@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = IS42S16160(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = IS42S16160(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/qmtech_wukong.py

@@ -72,13 +72,10 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K128M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/radiona_ulx3s.py

@@ -113,13 +113,11 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = False
+                phy              = self.sdrphy,
+                module           = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
+                size             = 0x40000000,
+                l2_cache_size    = kwargs.get("l2_size", 8192),
+                l2_cache_reverse = False
             )
 
         # Video ------------------------------------------------------------------------------------

litex_boards/targets/saanlima_pipistrello.py

@@ -179,13 +179,10 @@ class BaseSoC(SoCCore):
                 self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
             ]
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT46H32M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT46H32M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/scarabhardware_minispartan6.py

@@ -85,13 +85,11 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = AS4C16M16(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = False
+                phy              = self.sdrphy,
+                module           = AS4C16M16(sys_clk_freq, sdram_rate),
+                size             = 0x40000000,
+                l2_cache_size    = kwargs.get("l2_size", 8192),
+                l2_cache_reverse = False
             )
 
         # Video ------------------------------------------------------------------------------------

litex_boards/targets/siglent_sds1104xe.py

@@ -88,13 +88,10 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K64M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K64M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Etherbone --------------------------------------------------------------------------------

litex_boards/targets/sqrl_acorn.py

@@ -92,13 +92,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K512M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41K512M16(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # PCIe -------------------------------------------------------------------------------------

litex_boards/targets/sqrl_xcu1525.py

@@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT40A512M8(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT40A512M8(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
             # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
             platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")

litex_boards/targets/terasic_de0nano.py

@@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = IS42S16160(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = IS42S16160(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/terasic_de10lite.py

@@ -70,13 +70,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = IS42S16320(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = IS42S16320(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Video Terminal ---------------------------------------------------------------------------

litex_boards/targets/terasic_de10nano.py

@@ -81,13 +81,10 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = AS4C32M16(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = AS4C32M16(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Video Terminal ---------------------------------------------------------------------------

litex_boards/targets/terasic_de1soc.py

@@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = IS42S16320(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = IS42S16320(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
 # Build --------------------------------------------------------------------------------------------

litex_boards/targets/terasic_de2_115.py

@@ -65,13 +65,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = IS42S16320(self.clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = IS42S16320(self.clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
 # Build --------------------------------------------------------------------------------------------

litex_boards/targets/terasic_sockit.py

@@ -120,31 +120,15 @@ class BaseSoC(SoCCore):
         self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate)
 
         # SDR SDRAM --------------------------------------------------------------------------------
-        if mister_sdram == "xs_v22":
-            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
-            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
-            self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = W9825G6KH6(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
-            )
-
-        if mister_sdram == "xs_v24":
-            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
-            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
-            self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = AS4C32M16(sys_clk_freq, sdram_rate),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
-            )
+        sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
+        sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}
+        self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
+        self.add_sdram("sdram",
+            phy           = self.sdrphy,
+            module        = sdrphy_mod(sys_clk_freq, sdram_rate),
+            size          = 0x40000000,
+            l2_cache_size = kwargs.get("l2_size", 8192)
+        )
 
         # Video Terminal ---------------------------------------------------------------------------
         if with_video_terminal:

litex_boards/targets/trellisboard.py

@@ -132,13 +132,10 @@ class BaseSoC(SoCCore):
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J256M16(sys_clk_freq, "1:2"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J256M16(sys_clk_freq, "1:2"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/trenz_c10lprefkit.py

@@ -79,13 +79,10 @@ class BaseSoC(SoCCore):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.sdrphy,
-                module                  = MT48LC16M16(sys_clk_freq, "1:1"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.sdrphy,
+                module        = MT48LC16M16(sys_clk_freq, "1:1"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/trenz_tec0117.py

@@ -111,7 +111,6 @@ class BaseSoC(SoCCore):
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
                 module                  = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
-                origin                  = self.mem_map["main_ram"],
                 l2_cache_size           = 128,
                 l2_cache_min_data_width = 256,
             )

litex_boards/targets/xilinx_ac701.py

@@ -76,13 +76,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT8JTF12864(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT8JTF12864(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/xilinx_alveo_u250.py

@@ -78,13 +78,10 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 500e6,
                 is_rdimm         = True)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------

litex_boards/targets/xilinx_alveo_u280.py

@@ -77,13 +77,10 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 500e6,
                 is_rdimm         = True)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------

litex_boards/targets/xilinx_kc705.py

@@ -71,13 +71,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT8JTF12864(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT8JTF12864(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet ---------------------------------------------------------------------------------

litex_boards/targets/xilinx_kcu105.py

@@ -80,13 +80,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = EDY4016A(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = EDY4016A(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------

litex_boards/targets/xilinx_vc707.py

@@ -67,13 +67,10 @@ class BaseSoC(SoCCore):
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT8JTF12864(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT8JTF12864(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # PCIe -------------------------------------------------------------------------------------

litex_boards/targets/xilinx_vcu118.py

@@ -74,13 +74,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = EDY4016A(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = EDY4016A(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/xilinx_zcu104.py

@@ -75,13 +75,10 @@ class BaseSoC(SoCCore):
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/ztex213.py

@@ -83,13 +83,10 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
+                phy           = self.ddrphy,
+                module        = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Leds -------------------------------------------------------------------------------------