Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.

This commit is contained in:
Florent Kermarrec 2021-01-25 11:52:59 +01:00
parent 537f494cbb
commit 1e1bec10c4
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex_boards/targets/orangecrab.py
View File

@ -183,8 +183,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY(
pads = ddram_pads,
sys_clk_freq = sys_clk_freq,
cmd_delay = 0 if sys_clk_freq > 64e6 else 100,
dm_remapping = {0:1, 1:0})
cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):